学习并行操作的思想。
勘误001：
Page 17，模块图下方，“扫描频配置定为100Hz”应为10Hz。
勘误002：
Page 17，最后一行
“10ms”应为100ms；“2.5ms”应为25ms；（ps：这里用1000ms，每个led亮250ms效果比较明显）
源码如下：
/*************************************************
module name:led0_module.v
function:drive led on for 25ms; by yf.x
2014-11-3
**************************************************/
module led0_module(
CLK,RST_n,LED0
); input CLK,RST_n;
output LED0; /****************************************/
//DE2-115 has 50MHz oc,so 50M*1s=50_000_000
parameter T1000ms='d50_000_000;
/****************************************/
//1000ms counter reg [:]count1; always @(posedge CLK or negedge RST_n)
if(!RST_n)
count1<='d0;
else if(count1==T1000ms)
count1<='d0;
else
count1<=count1+'b1; /***************************************/
// control led on for 100ms reg rLED; always @(posedge CLK or negedge RST_n)
if(!RST_n)
rLED<='b0;
else if(count1>='d0 && count1<26'd1_2500_000)
rLED<='b1;
else
rLED<='b0; /***************************************/ assign LED0=rLED; endmodule
/*************************************************
module name:led1_module.v
function:drive led on for 25ms; by yf.x
2014-11-3
**************************************************/
module led1_module(
CLK,RST_n,LED1
); input CLK,RST_n;
output LED1; /****************************************/
//DE2-115 has 50MHz oc,so 50M*1=50_000_000
parameter T1000ms='d50_000_000;
/****************************************/
//1000ms counter reg [:]count1; always @(posedge CLK or negedge RST_n)
if(!RST_n)
count1<='d0;
else if(count1==T1000ms)
count1<='d0;
else
count1<=count1+'b1; /***************************************/
// control led on for 100ms reg rLED; always @(posedge CLK or negedge RST_n)
if(!RST_n)
rLED<='b0;
else if(count1>='d1_2500_000 && count1<26'd2_5000_000)
rLED<='b1;
else
rLED<='b0; /***************************************/ assign LED1=rLED; endmodule
/*************************************************
module name:led2_module.v
function:drive led on for 25ms; by yf.x
2014-11-3
**************************************************/
module led2_module(
CLK,RST_n,LED2
); input CLK,RST_n;
output LED2; /****************************************/
//DE2-115 has 50MHz oc,so 50M*1=50_000_000
parameter T1000ms='d50_000_000;
/****************************************/
//1000ms counter reg [:]count1; always @(posedge CLK or negedge RST_n)
if(!RST_n)
count1<='d0;
else if(count1==T1000ms)
count1<='d0;
else
count1<=count1+'b1; /***************************************/
// control led on for 100ms reg rLED; always @(posedge CLK or negedge RST_n)
if(!RST_n)
rLED<='b0;
else if(count1>='d2_5000_000 && count1<26'd3_7500_000)
rLED<='b1;
else
rLED<='b0; /***************************************/ assign LED2=rLED; endmodule
/*************************************************
module name:led3_module.v
function:drive led on for 25ms; by yf.x
2014-11-3
**************************************************/
module led3_module(
CLK,RST_n,LED3
); input CLK,RST_n;
output LED3; /****************************************/
//DE2-115 has 50MHz oc,so 50M*1=50_000_000
parameter T1000ms='d50_000_000;
/****************************************/
//1000ms counter reg [:]count1; always @(posedge CLK or negedge RST_n)
if(!RST_n)
count1<='d0;
else if(count1==T1000ms)
count1<='d0;
else
count1<=count1+'b1; /***************************************/
// control led on for 100ms reg rLED; always @(posedge CLK or negedge RST_n)
if(!RST_n)
rLED<='b0;
else if(count1>='d3_7500_000 && count1<26'd50_000_000)
rLED<='b1;
else
rLED<='b0; /***************************************/ assign LED3=rLED; endmodule
/*********************************
module name:top.v
function:control 4 led on for 250ms
(for DE2-115)
pin assignments:
---------------------------------
CLK----------------------CLOCK_50
RST_n--------------------KEY[0]
LED(0-3)-----------------LEDG[0-3]
--------------------------------- yf.x
2014-11-03
**********************************/ module top(
CLK,RST_n,LED
); input CLK,RST_n;
output [:]LED; /*********************************/ wire [:]LED_out; led0_module u0(
.CLK(CLK),
.RST_n(RST_n),
.LED0(LED_out[])
); /*********************************/ led1_module u1(
.CLK(CLK),
.RST_n(RST_n),
.LED1(LED_out[])
); /*********************************/ led2_module u2(
.CLK(CLK),
.RST_n(RST_n),
.LED2(LED_out[])
); /*********************************/ led3_module u3(
.CLK(CLK),
.RST_n(RST_n),
.LED3(LED_out[])
); /*********************************/ assign LED=LED_out; endmodule