UVM Top Testbench

top testbench在top_tb中包含进所有的文件，将DUT放在top_tb中（例化DUT），连接好各个端口，提供clk时钟和rst_n复位信号。最主要的是要给组件中的虚接口设置接口，一般是给driver和monitor的虚接口例化接口。初始化run_test()使其自动启动UVM仿真。用config机制配置内部变量。如例：

 `timescale 1ns/1ps

 `include "uvm_macros.svh"

 import uvm_pkg::*;

 `include "my_if.sv"

 `include "my_transaction.sv"

 `include "my_sequencer.sv"

 `include "my_driver.sv"

 `include "my_monitor.sv"

 `include "my_agent.sv"

 `include "my_model.sv"

 `include "my_scoreboard.sv"

 `include "my_sequence.sv"

 `include "my_env.sv"

 `include "base_test.sv"

 module top_tb;

 reg clk;

 reg rst_n;

 reg[:] rxd;

 reg rx_dv;

 wire[:] txd;

 wire tx_en;

 my_if input_if(clk, rst_n);

 my_if output_if(clk, rst_n);

 dut my_dut(.clk(clk),

            .rst_n(rst_n),

            .rxd(input_if.data),

            .rx_dv(input_if.valid),

            .txd(output_if.data),

            .tx_en(output_if.valid));

 initial begin

    clk = ;

    forever begin

       # clk = ~clk;

    end

 end

 initial begin

    rst_n = 'b0;

    #;

    rst_n = 'b1;

 end

 initial begin

    run_test("base_test");

 end

 initial begin

    uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.drv", "vif", input_if);

    uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.mon", "vif", input_if);

    uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.o_agt.mon", "vif", output_if);

 end

 endmodule

参考文献：

[1] 测试平台说明. http://www.asicdv.com/uvm_scan.asp?id=39.

[2] 张强. UVM实战. 机械工业出版社. 2014.07.