筛选最小值---verilog
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: chensimin
//
// Create Date: 2018/12/07 15:30:20
// Design Name:
// Module Name: aes_dru
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////// module aes_dru ( input wire clk,
input wire rst ); //--------------------------------------------------------------------- //计数器，方便对生成的序列进行定位，仿真时，生成信号源的好思路 reg [:] cnt_for_serin = ; always @ (posedge clk or posedge rst)
begin
if(rst)
cnt_for_serin <= ;
else
cnt_for_serin <= cnt_for_serin + 'b1;
end //--------------------------------------------------------------------- //生成serin序列 reg serin = ; always @ (posedge clk or posedge rst)
begin
if(rst)
serin <= ;
else
begin
case(cnt_for_serin)
: serin <= 'b1;
: serin <= 'b0;
: serin <= 'b1;
: serin <= 'b0;
: serin <= 'b1;
default: serin <= serin;
endcase
end
end //--------------------------------------------------------------------- reg [:] inffs = ; always @ (posedge clk or posedge rst)
begin
if(rst)
inffs <= ;
else
inffs <= {inffs[:], serin};
end //--------------------------------------------------------------------- //边沿检测可以检测上升沿和下降沿 assign edge_detect = ^inffs[:]; //--------------------------------------------------------------------- //计算出两个脉冲之间的时钟周期 reg [:] min_cntr = ; always @ (posedge clk or posedge rst)
begin
if(rst)
min_cntr <= ;
else if(edge_detect)
min_cntr <= ;
else
min_cntr <= min_cntr + ;
end //--------------------------------------------------------------------- //对边沿脉冲进行计数 reg [:] update_cntr = ; always @ (posedge clk or posedge rst)
begin
if(rst)
update_cntr <= ;
else if(edge_detect)
update_cntr <= update_cntr + 'b1;
end //--------------------------------------------------------------------- //当边沿脉冲数满后，产生一个叫update_min的脉冲 wire update_min; assign update_min = update_cntr == {{'b1}}; //--------------------------------------------------------------------- //当updata_min脉冲到来时，最小值设定为全1，new_min成为更新min_capture的条件 reg [:] min_capture = ; always @ (posedge clk or posedge rst)
begin
if(rst)
min_capture <= ;
else if(edge_detect)
begin
if(update_min)
min_capture <= {{'b1}};
else if(new_min)
min_capture <= min_cntr;
end
end assign new_min = min_cntr < min_capture; //--------------------------------------------------------------------- //当结束完一个计数周期后，用min_hold 锁存本周期的最小值 reg [:] min_hold = ; always @ (posedge clk or posedge rst)
begin
if(rst)
min_hold <= ;
else if (edge_detect & update_min)
min_hold <= min_capture;
end //--------------------------------------------------------------------- // reg [:] sample_cntr = ; always @ (posedge clk or posedge rst)
begin
if(rst)
sample_cntr <= ;
else if (edge_detect | (sample_cntr >= min_hold))
sample_cntr <= ;
else
sample_cntr <= sample_cntr + ;
end //--------------------------------------------------------------------- endmodule /* add_force {/aes_dru/clk} -radix hex {1 0ns} {0 25000ps} -repeat_every 50000ps
add_force {/aes_dru/rst} -radix hex {1 0ns} {0 100ns} */
仿真结果：