NetFPGA-1G-CML点亮 LED

前言

用vivado建立工程的时候选择的型号为：XC7K325tffg676-1

在以下代码文件中，仿真与设计都没有问题。在xdc文件中的时钟约束与锁相环配置中还存在问题，没有寻找到解决办法

使用手册链接

原理图链接

---

design文件

`timescale 1ns / 1ps

module led_des(output reg[1:0] led = 2'b01,

                input wire CLK);

    reg[32:0] count = 0;

    parameter T1MS = 3;

    always@(posedge CLK)

    begin

        count <= count + 1;

        if(count > T1MS)

        begin

            count <= 0;

            if(led == 2'b01)

            begin

                led <= 2'b10;

            end

            else

            begin

                led <= 2'b01;

            end

        end

    end

endmodule

sim仿真文件

`timescale 1ns / 1ps

module led_sim;

reg CLK;

wire [1:0] led;

initial

begin

    #100

    CLK = 0;

end

always #10 CLK = ~CLK;

led_des led_des_inst(

    .CLK(CLK),

    .led(led)

);

endmodule

xdc约束文件

create_clock -period 100.000 -name CLK -waveform {0.000 50.000} [get_ports CLK]

#create_clock -name clk100MHZ -period 10.0 [get_ports {CLK}]

set_property PACKAGE_PIN E18 [get_ports {CLK}]

set_property IOSTANDARD LVCMOS33 [get_ports {CLK}]

set_property PACKAGE_PIN E17 [get_ports {led[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]

set_property PACKAGE_PIN F17 [get_ports {led[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]