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使用了状态机,增加了可读性和用户体验。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
led : out STD_LOGIC_VECTOR ( downto );
an : out STD_LOGIC_VECTOR ( downto );
seg : out STD_LOGIC_VECTOR ( downto ));
end main; architecture Behavioral of main is
signal sclk: std_logic;
signal now_state,next_state: std_logic_vector( downto );
signal ledt: std_logic_vector( downto );
signal led_state: std_logic_vector( downto );
signal cnt0:integer:=;
signal cnt1:integer:=;
signal cnt2:integer:=;
signal disp_main:integer:=;
signal disp_branch:integer:=;
signal display:integer;
signal time_main:integer;
signal time_main_l:integer;
signal time_main_h:integer;
signal time_branch:integer;
signal time_branch_l:integer;
signal time_branch_h:integer;
signal time_long:integer:=;
constant red_time:integer:=;
constant green_time:integer:=;
constant yellow_time:integer:=;
signal an_sel: integer;
begin
led()<=led_state();
led()<=led_state();
led()<=led_state();
led()<=led_state();
led()<=led_state();
led()<=led_state();
process(clk)
begin
if(clk'event and clk='') then
if(cnt0=)then
cnt0<=;
sclk<=not sclk;
else
cnt0<=cnt0+;
end if;
end if;
end process; process(clk)
begin
if(clk'event and clk='') then
if(cnt2=) then
cnt2<=;
if(an_sel=)then
an_sel<=;
else
an_sel<=an_sel+;
end if;
else
cnt2<=cnt2+;
end if;
end if;
end process; process(now_state)
begin
case now_state is
when ""=>time_long<=green_time;ledt<="";next_state<="";
when ""=>time_long<=yellow_time;ledt<="";next_state<="";
when ""=>time_long<=green_time;ledt<="";next_state<="";
when ""=>time_long<=yellow_time;ledt<="";next_state<="";
when others=>time_long<=green_time;ledt<="";next_state<="";
end case;
end process; process(rst,sclk)
begin
if(rst='') then
now_state<="";
led_state<="";
elsif(sclk'event and sclk='') then
led_state()<=ledt();
led_state()<=ledt();
led_state()<=ledt();
led_state()<=ledt();
led_state()<=ledt();
led_state()<=ledt();
if(cnt1=time_long) then
now_state<=next_state;
cnt1<=;
else
cnt1<=cnt1+;
end if;
end if;
end process; process(sclk,led_state,rst,cnt1)
begin
if (rst='')then
disp_main<=red_time;
disp_branch<=green_time;
elsif(sclk'event and sclk='') then
if(disp_main=)then
if(led_state()='')then
disp_main<=green_time;
elsif(led_state()='')then
disp_main<=yellow_time;
elsif(led_state()='')then
disp_main<=red_time;
end if;
else
disp_main<=disp_main - ;
end if;
if(disp_branch=)then
if(led_state()='')then
disp_branch<=green_time;
elsif(led_state()='')then
disp_branch<=yellow_time;
elsif(led_state()='')then
disp_branch<=red_time;
end if;
else
disp_branch<=disp_branch - ;
end if;
end if;
end process; process(an_sel,disp_main,disp_branch)
begin
time_main<=disp_main;
if(time_main>=)then
time_main_h<=;
time_main_l<=time_main-;
else
time_main_h<=;
time_main_l<=time_main;
end if;
time_branch<=disp_branch;
if(time_branch>=)then
time_branch_h<=;
time_branch_l<=time_branch-;
else
time_branch_h<=;
time_branch_l<=time_branch;
end if;
case an_sel is
when =>an<="";display<=time_main_l;
when =>an<="";display<=time_main_h;
when =>an<="";display<=time_branch_l;
when =>an<="";display<=time_branch_h;
when others=>null;
end case;
case display is
when =>seg<=b"";
when =>seg<=b"";
when =>seg<=b"";
when =>seg<=b"";
when =>seg<=b"";
when =>seg<=b"";
when =>seg<=b"";
when =>seg<=b"";
when =>seg<=b"";
when =>seg<=b"";
when others=>null;
end case;
end process;
end Behavioral;