视频信号中xyz的提取
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: chensimin
//
// Create Date: 2019/01/15 11:52:24
// Design Name:
// Module Name: detect_video
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////// module detect_video( input wire clk,
input wire rst, output reg [:] vid_out = , output wire xyz ); //------------------------------------------------------------------ reg [:] i = ; always @(posedge clk or posedge rst)
begin
if(rst)
begin
i <= ;
vid_out <= 'h000;
end
else
begin
case(i)
:
begin
i <= i + 'b1;
vid_out <= 'h000;
end
:
begin
i <= i + 'b1;
vid_out <= 'h3FF;
end
:
begin
i <= i + 'b1;
vid_out <= 'h000;
end
:
begin
i <= i + 'b1;
vid_out <= 'h000;
end
:
begin
i <= i + 'b1;
vid_out <= 'h274;
end
:
begin
i <= i + 'b1;
vid_out <= 'h000;
end
:
begin
i <= i + 'b1;
vid_out <= 'h080;
end
default:
begin
i <= i;
vid_out <= 'h000;
end
endcase
end
end detect_xyz U0 ( .clk(clk),
.rst(rst),
.vid_in(vid_out),
.xyz(xyz)
); endmodule /* add_force {/detect_video/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps
add_force {/detect_video/rst} -radix hex {1 0ns} {0 200ns} */
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: chensimin
//
// Create Date: 2019/01/15 13:30:22
// Design Name:
// Module Name: detect_xyz
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////// module detect_xyz ( input wire clk,
input wire rst,
input wire [:] vid_in, output reg xyz ); //------------------------------------------------------------------ reg [:]vid_in_delay_0 = ;
reg [:]vid_in_delay_1 = ; reg xyz = ; always @(posedge clk or posedge rst)
begin
if(rst)
begin
vid_in_delay_0 <= 'h000;
vid_in_delay_1 <= 'h000;
end else
begin
vid_in_delay_0 <= vid_in;
vid_in_delay_1 <= vid_in_delay_0; if( vid_in_delay_1 == 'h3FF && vid_in_delay_0 == 10'h000
&& vid_in == 'h000)
xyz <= ;
else
xyz <= ;
end
end endmodule
仿真结果：