在Xilinx ISE中使用Synopsys Synplify 综合比较方便，但有时会出现如下错误：
"ERROR:NgdBuild: - logical block ' ' with type ' ' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol ' is not supported in target 'virtex5'."
可以在综合选项中选择Synplify/Verilog，避免上述错误。原选择为Synplify/Verilog-VHDL. 相当于只选择一种HDL语言进行综合。
之前相关的参考链接有：
1. https://www.xilinx.com/support/answers/38262.html
2. https://forums.xilinx.com/t5/Implementation/NgdBuild-604-error-with-ISE-12-3/td-p/120918
3. https://www.edaboard.com/showthread.php?85318-plz-help-me-solve-these-erors-in-xilinx-project