Verilog中已有一些建立好的逻辑门和开关的模型。在所涉及的模块中，可通过实例引用这些门与开关模型，从而对模块进行结构化的描述。
逻辑门:
and (output,input,...)
nand (output,input,...)
or (output,input,...)
nor (output,input,...)
xor (output,input,...)
xnor (output,input,...)
缓冲器和与非门
buf (output,...,input)
not (output,...,input)
三态门：
bufif0 (output,input,enable)
bufif1 (output,input,enable)
notif0 (output,input,enable)
notif1 (output,input,enable)
MOS开关
nmos (output,input,enable)
pmos (output,input,enable)
rnmos (output,input,enable)
rpmos (output,input,enable)
CMOS开关
cmos (output,input,Nenable,Penable)
rcmos (output,input,Nenable,Penable)
双向开关：
tran (inout,inout2)
rtran (inout,inout2)
双向可控开关
tranif0 (inout1,inout2,control)
tranif1 (inout1,inout2,control)
rtranif0 (inout1,inout2,control)
rtranif1 (inout1,inout2,control)
上拉源和下拉源
pullup (output)
pulldown (output)
以下为上述门电路的真值表：
其中逻辑值L和H代表部分未知值。L表示0或者Z，H表示1或者Z；
附表1 与门真值表
| and | 0 | 1 | x | z |
| 0 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | x | x |
| x | 0 | x | x | x |
| z | 0 | x | x | x |
附表2 与非门真值表
| nand | 0 | 1 | x | z |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 1 | 0 | x | x |
| x | 1 | x | x | x |
| z | 1 | x | x | x |
附表3 或门真值表
| or | 0 | 1 | x | z |
| 0 | 0 | 1 | x | x |
| 1 | 1 | 1 | 1 | 1 |
| x | x | 1 | x | x |
| z | x | 1 | x | x |
附表4 或非门真值表
| nor | 0 | 1 | x | z |
| 0 | 1 | 0 | x | x |
| 1 | 0 | 0 | 0 | 0 |
| x | x | 0 | x | x |
| z | x | 0 | x | x |
附表5 异或门真值表
| xor | 0 | 1 | x | z |
| 0 | 0 | 1 | x | x |
| 1 | 1 | 0 | x | x |
| x | x | x | x | x |
| z | x | x | x | x |
附表6 同或门真值表
| xor | 0 | 1 | x | z |
| 0 | 1 | 0 | x | x |
| 1 | 0 | 1 | x | x |
| x | x | x | x | x |
| z | x | x | x | x |
附表7 缓冲器及与非门真值表
| buf | not | |||
| Input | Output | Input | Output | |
| 0 | 0 | 0 | 1 | |
| 1 | 1 | 1 | 0 | |
| x | x | x | x | |
| z | x | z | x |
附表8 缓冲器使能端真值表
| Bufif0 | Enable | Bufif1 | Enable | ||||||||
| 0 | 1 | x | z | 0 | 1 | x | z | ||||
D A T A | 0 | 0 | z | L | L | D A T A | 0 | z | 0 | L | L |
| 1 | 1 | z | H | H | 1 | z | 1 | H | H | ||
| x | x | z | x | x | x | z | x | x | x | ||
| z | x | z | x | x | z | z | x | x | x |
附表9 缓冲器非门使能端真值表
| notif0 | Enable | notif1 | Enable | ||||||||
| 0 | 1 | x | z | 0 | 1 | x | z | ||||
D A T A | 0 | 1 | z | H | H | D A T A | 0 | z | 1 | H | H |
| 1 | 0 | z | L | L | 1 | z | 0 | L | L | ||
| x | x | z | x | x | x | z | x | x | x | ||
| z | x | z | x | x | z | z | x | x | x |
附表10 MOS型控制端真值表
Pmos Rpmos | Control | Nmos Rnmos | Control | ||||||||
| 0 | 1 | x | z | 0 | 1 | x | z | ||||
D A T A | 0 | 0 | z | L | L | D A T A | 0 | z | 0 | L | L |
| 1 | 1 | z | H | H | 1 | z | 1 | H | H | ||
| x | x | z | x | x | x | z | x | x | x | ||
| z | z | z | z | z | z | z | z | z | z |
规则：
1）缓冲门、非门都可以有多个输出，但是这些输出值都是相同的。
2）当nmos，pmos，cmos, tran, tranif0, tranif1类型的开关开启时，信号从输入到输出并不改变其强度。
3）当有电阻的开关，如rnmos, rpmos, rcmos, rtran, rtranif0, rtranif1类型的开关，开启式，信号从输入到输出会改变其强度。
| Strength | 减至 |
| supply | pull |
| strong | pull |
| pull | weak |
| large | medium |
| weak | medium |
| medium | small |
| small | small |
| highz | highz |