fpga图像处理实战-双线性插值算法

FPGA实现

        

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2024/08/29 19:10:23
// Design Name: 
// Module Name: image_line_buffer
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module image_line_buffer(
    input                               clk                        ,
    input                               rst                        ,
    input              [  11: 0]        img_width                  ,
    input                               valid_i                    ,
    input              [  23: 0]        img_data_i                 ,
    output