关于verilog不能处理数组端口的解决方法

---

即在Verilog中，不支持如下的端口定义：

module divider_common#
(
     parameter                                  CHAN_NUM                  = 8    // 通道数
    ,parameter                                  CHAN_DW                   = 8    // 数据位宽
)
(
     input                                      sys_clk
    ,input                                      sys_rst
    
    ...
    
    ,input                                      i_dat_vld      [0:CHAN_NUM-1]
    ,input  [CHAN_DW-1:0]                       i_dat          [0:CHAN_NUM-1]

    ...

    ,output                                     o_dat_vld      [0:CHAN_NUM-1]
    ,output [CHAN_DW-1:0]                       o_dat          [0:CHAN_NUM-1]
);

针对上述情况，更改端口定义方式：即从数组定义方式变为大位宽定义

module divider_common#
(
     parameter                                  CHAN_NUM                  = 8    // 通道数
    ,parameter                                  CHAN_DW                   = 8    // 数据位宽
)
(
     input                                      sys_clk
    ,input                                      sys_rst
    
    ...
    
    ,input  [CHAN_NUM-1:0]                      i_dat_vld
    ,input  [CHAN_NUM*CHAN_DW-1:0]              i_dat

    ...

    ,output [CHAN_NUM-1:0]                      o_dat_vld
    ,output [CHAN_NUM*CHAN_DW-1:0]              o_dat
);

对于input端口

    genvar i;
    
    wire                             data_in_vld      [0:CHAN_NUM-1]  ;
    wire  [CHAN_DW-1:0]              data_in          [0:CHAN_NUM-1]  ;

    // input 大位宽转数组
    generate
        for (i = 0; i < CHAN_NUM; i = i + 1) begin
            assign data_in_vld[i] = i_dat_vld[i*1 +: 1];
            assign data_in[i] = i_dat[i*CHAN_DW +: CHAN_DW];
        end
    endgenerate

对于output端口

    genvar i;
    
    reg                             data_out_vld      [0:CHAN_NUM-1]  ;
    reg  [CHAN_DW-1:0]              data_out          [0:CHAN_NUM-1]  ;

    // input 大位宽转数组
    generate
        for (i = 0; i < CHAN_NUM; i = i + 1) begin
            assign o_dat_vld[i*1 +: 1] = data_out_vld[i];
            assign o_dat[i*CHAN_DW +: CHAN_DW] = data_out[i];
        end
    endgenerate

    ...

    generate
        for (i = 0; i < CHAN_NUM; i = i + 1) begin
            always@ (posedge sys_clk) begin
                data_out_vld[i] <= ...;
                data_out <= ...;
            end
        end
    endgenerate