问题描述
我正在使用Xilinx ISE，并使用CORE Generator&体系结构向导.
I'm using Xilinx ISE and generated a memory using the CORE Generator & Architecture Wizard.
问题在于它创建了一个写使能信号(wea)作为STD_LOGIC_VECTOR(0至0)，并导致类型不匹配:
The problem is that it created a write enable signal (wea) as a STD_LOGIC_VECTOR(0 downto 0) and that results in a type mismatch:
如何将std_logic的encnt转换为一点std_logic_vector?
How can I cast encnt, which is std_logic, to a one bit std_logic_vector?
(ISE不允许我从内存文件中更改wea.)
(ISE doesn't allow me to change wea from the file of memory.)
推荐答案
这是使用这些IP块的一种非常常见的情况.您可以像这样轻松关联std_logic信号:
This is a pretty common scenario with these IP blocks. You can easily associate your std_logic signal like this:
wea(0) => encnt,
您不是在整体上关联wea，而是只是关联了一个元素(0).由于wea仅具有一个元素，因此将分配整个矢量.
Instead of associating wea as a whole, you are just associating that one element (0). As wea only has one element, this assigns the whole vector.
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