问题描述
我具有基于ARM的SoC的以下规范:
I have the following specifications of an ARM based SoC:
- L1数据缓存= 32 KB，64 B/行，2-WAY，LRU
- L2缓存= 1 MB，64 B/行，16路
- L1数据TLB(用于负载):32个条目，完全关联
- L2数据TLB:512个条目，四路
- PDE缓存:16个条目(每1 MB虚拟空间一个条目)
我想知道什么是PDE缓存?我想这与TLB类似，但我不确定.
And I wonder what is the PDE cache? I guess it's something similar to TLB, but I'm not sure.
答案
似乎PDE(页面目录条目)是中级表格浏览缓存，它的确可以与TLB分开实现.
Answer
It seems that PDE (Page Directory Entry) is Intermediate table walk cache which indeed can be implemented separately from TLB.
推荐答案
这很有趣.在Cortex-A15，Cortex-A57文档以及ARMv7和ARMv8编程指南中，ARM并未提及该PDE缓存的存在.
That's interesting. ARM does not name the existence of this PDE cache in Cortex-A15, Cortex-A57 documentations and ARMv7 and ARMv8 programming guides.
PDE通常代表页面目录条目，因此这可能是专用缓存，用于存储这些条目并在进行地址转换时写入TTBR寄存器.
PDE generally stands for Page Directory Entry so this may be a dedicated cache to store these entries and write the TTBR register when doing an address translation.
ARM有一些与ASID字段(地址空间标识符)和VMID字段(虚拟机标识符)相关联的中间表遍历缓存"，因此看来PDE缓存和中间表遍历缓存是相关的.在文档中，中间表遍历缓存"存储翻译表条目的中间级别...因此，这很可能是页面目录条目.
ARM has some "intermediate table walk caches" that are associated with an ASID field (address space identifier) and VMID field (virtual machine identifier) so it seems like PDE cache and intermediate table walk cache are related. In the documentation, "intermediate table walk caches" store intermediate levels of translation table entries ... so this may well be the page directory entries.
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