Verilog MIPS32 CPU（九）-- 顶层文件

`timescale 1ns / 1ps

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// Company:

// Engineer:

//

// Create Date: 04/28/2017 07:27:12 PM

// Design Name:

// Module Name: Interfaces

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module Interface(

        input clk,

        input rst,

        output [:] o_seg,AN

        );

//    wire [7:0] o_seg,AN;

    wire [:] instr,rdata1,rdata2;

    wire [:] pc;

    wire [:] reg_data;

    wire reg_wena,ram_wena,pc_ena;

    wire [:] ram_addr;

    wire [:] alu_op;

    wire [:] alu_r;

    wire [:] rs,rt,rd;

    wire [:] hi,lo,cop_data;

    parameter    ENA        =    'b1;

    parameter     DIS        =    'b0;

    wire [:] pc_in,alu_a,alu_b;

    wire [:] ram_data;

    wire [:] wdata,exc_addr;

    wire [:] mult_hi,mult_lo,div_hi,div_lo;

    wire [:] waddr;

    wire [:] cause;

    wire z,c,o,n;

    wire mtc0,eret;

    wire [:] mdu;

    wire [:] IRAdd = pc>>;

    wire [:] mul_out;

    wire [:] watch_out;

//    wire [31:0] watch_out2=call_code;

    wire seg7_cs,teq_exc;

    wire scan_dir;

    drive IR(.a(IRAdd[:]), .spo(instr));

    pcreg pcreg(

        clk,

        rst,

        pc_ena,

        pc_in,

        pc);

    alu alu(

        alu_a,

        alu_b,

        alu_op,

        alu_r,

        z,c,n,o);

    RegFiles regfiles(

        clk,

        rst,

        reg_wena,

        rs,

        rt,

        waddr,

        wdata,

        rdata1,

        rdata2

        );

      CP0 CP0(

          clk,rst,teq_exc,mtc0,

          pc,

          rd,rdata2,

          eret,cause,

          cop_data,exc_addr);

      ram ram(

          clk,

          ram_wena,

          ram_addr[:],

          reg_data,

          ram_data,

          watch_out

          );

    seg7x16 seg7x16(

        clk,rst,

        watch_out,

        o_seg,AN);

    MDU MDU(

        .mdu(mdu),

        .clk(clk),.rst(rst),

        .mul_out(mul_out),

        .rdata1(rdata1),.rdata2(rdata2),

        .hi(hi),.lo(lo),

        .pc_ena(pc_ena));

    CtrlUnit CtrlUnit(

        .instr(instr),

        .rdata1(rdata1),

        .rdata2(rdata2),

        .pc(pc),

        .clk(clk),

        .ram_data(ram_data),

        .mul_out(mul_out[:]),

        .rs(rs),.rt(rt),.rd(rd),

        .hi(hi),.lo(lo),

        .cop_data(cop_data),

        .exc_addr(exc_addr),

        .teq_exc(teq_exc),

        .mtc0(mtc0),.eret(eret),

        .mdu(mdu),

        .cause(cause),

        .reg_wena(reg_wena),.ram_wena(ram_wena),

        .waddr(waddr),.ram_addr(ram_addr),

        .wdata(wdata),.reg_data(reg_data),

        .pc_in(pc_in),

        .alu_a(alu_a),.alu_b(alu_b),.alu_r(alu_r),

        .alu_op(alu_op));

endmodule