从 RAM DEPTH 开始的地址宽度

问题描述

我正在实现一个可配置的 DPRAM，其中 RAM DEPTH 是参数.

I am implementing a configurable DPRAM where RAM DEPTH is the parameter.

如何从内存深度确定地址宽度?

How to determine ADDRESS WIDTH from RAM DEPTH?

我知道 RAM DEPTH = 2 ^ (ADDRESS WIDTH) 的关系

I know the relation RAM DEPTH = 2 ^ (ADDRESS WIDTH)

即地址宽度 = log (base 2) RAM DEPTH.

i.e ADDRESS WIDTH = log (base 2) RAM DEPTH.

如何在Verilog中实现log(base 2)函数?

How to implement the log (base 2) function in Verilog?

推荐答案

$clog2 系统任务已添加到 Verilog (IEEE Std 1800-2005) 的 SystemVerilog 扩展中.这将返回一个整数，其值为对数基数 2 的上限.DEPTH 不必是 2 的幂.

The $clog2 system task was added to the SystemVerilog extension to Verilog (IEEE Std 1800-2005). This returns an integer which has the value of the ceiling of the log base 2. The DEPTH need not be a power of 2.

module tb;

parameter DEPTH = 5;
parameter WIDTH = $clog2(DEPTH);

initial begin
    $display("d=%0d, w=%0d", DEPTH, WIDTH);
    #5 $finish;
end

endmodule

运行模拟将显示:

d=5, w=3

但是，我不知道支持 $clog2 的综合工具.如果你需要综合你的代码，你可以使用function.这是从 IEEE 1364-2001 Std 复制而来的，但网络上还有其他版本:

However, I do not know of a synthesis tool which supports $clog2. If you need to synthesize your code, you can use a function. This was copied from the IEEE 1364-2001 Std, but there are other versions floating around the web:

function integer clogb2;
    input [31:0] value;
    begin
        value = value - 1;
        for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
            value = value >> 1;
        end
    end
endfunction

我的经验是，使用 function 比使用可合成代码更麻烦.它给设计流程中的其他工具(linter、等效检查器等)造成了问题.

My experience has been that using the function is more trouble than it's worth for synthesizable code. It has caused problems for other tools in the design flow (linters, equivalence checkers, etc.).

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