问题描述
使用像Intel optane DCPMM这样的永久性内存时,如果在执行movnt指令时系统崩溃(断电),重启后是否有可能看到部分结果?
When using persistent memory like Intel optane DCPMM, is it possible to see partial result after reboot if system crash(power outage) in execution of movnt instruction?
针对:
- 4或8字节的
movnti
,x86可以保证原子用于其他目的吗? - 16字节SSE
movntdq
/movntps
不能保证是原子的,但实际上可能在支持持久性内存的CPU上. - 32字节AVX
vmovntdq
/vmovntps
- 64字节AVX512
vmovntdq
/vmovntps
全线存储 - 额外的问题:
MOVDIR64B
已保证64字节在支持它和DC-PM的未来CPU上写原子性.例如蓝宝石急流至强/老虎湖/特里蒙特.
- 4 or 8 byte
movnti
which x86 guarantees atomic for other purposes? - 16-byte SSE
movntdq
/movntps
which aren't guaranteed atomic but which in practice probably are on CPUs supporting persistent memory. - 32-byte AVX
vmovntdq
/vmovntps
- 64-byte AVX512
vmovntdq
/vmovntps
full-line stores - bonus question:
MOVDIR64B
which has guaranteed 64-byte write atomicity, on future CPUs that support it and DC-PM. e.g. Sapphire Rapids Xeon / Tiger Lake / Tremont.
movntpd
与 movntps
相同.
相关问题:
推荐答案
x86在全局可观察性和持久性方面的原子性保证是相同的.这意味着以下操作始终是原子的:
Atomicity guarantees on x86 in global observability and persistency are the same. This means that the following operations are persistently atomic:
- 没有跨越8字节边界到任何有效内存类型的位置的存储uop,并且
-
MOVDIR64B
.
此外,以下操作始终是原子的:
In addition, the following operations are persistently atomic:
- 刷新缓存行(
CLFLUSH
或CLFLUSHOPT
), - 缓存行写回(
CLWB
)和 - 非体系结构缓存行逐出.
- 英特尔处理器上的完整写合并缓冲区刷新.WCB的存在和大小以及冲洗的原因是特定于实现的.请参阅:将英特尔非临时性商店订购到相同的缓存行.
- A cache line flush (
CLFLUSH
orCLFLUSHOPT
), - A cache line writeback (
CLWB
), and - A non-architectural cache line eviction.
- A full write-combining buffer flush on Intel processors. The presence and size of WCBs and the causes of flush are implementation-specific. See: Ordering of Intel non-temporal stores to the same cache line.
对于其他所有内容,包括64字节AVX512 vmovntdq
/ vmovntps
全线存储,都没有体系结构上的持久性原子保证.
There is no architectural persistent atomicity guarantee for everything else, including 64-byte AVX512 vmovntdq
/ vmovntps
full-line stores.
这些保证适用于异步DRAM刷新(ADR)平台和增强型异步DRAM刷新(eADR)平台.(在eADR上,缓存层次结构位于持久性域中.请参阅:构建具有可靠性可用性和可维护性的持久性内存应用程序.)
These guarantees apply to Asynchronous DRAM Refresh (ADR) platforms and Enhanced Asynchronous DRAM Refresh (eADR) platforms. (On eADR, the cache hierarchy is in the persistence domain. See: Build Persistent Memory Applications with Reliability Availability and Serviceability.)
此答案基于我与Andy Rudoff(英特尔)的私人通信.
This answer is based on my private correspondence with Andy Rudoff (Intel).
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