x86上的两个后续CPU存储是否已刷新到高速缓存中以保持顺序?

问题描述

假定有两个线程分别在x86 CPU0和CPU1上运行.在CPU0上运行的线程执行以下命令:

Assume there are two threads running on x86 CPU0 and CPU1 respectively. Thread running on CPU0 executes the following commands:

A=1
B=1

包含最初由CPU1拥有的A和包含由CPU0拥有的B的高速缓存行.

Cache line containing A initially owned by CPU1 and that containing B owned by CPU0.

我有两个问题:

1. 如果我理解正确，那么两个存储区都将放入CPU的存储区缓冲区中.但是，对于第一个存储区A=1，必须使CPU1的高速缓存无效，而第二个存储区B=1可以立即被刷新，因为CPU0拥有包含它的高速缓存行.我知道x86 CPU遵守存储订单.这是否意味着B=1不会在A=1之前写入缓存?

1. If I understand correctly, both stores will be put into CPU’s store buffer. However, for the first store A=1 the cache of CPU1 must be invalidated while the second store B=1 can be flushed immediately since CPU0 owns the cache line containing it. I know that x86 CPU respects store orders. Does that mean that B=1 will not be written to the cache before A=1?

假定在CPU1中执行以下命令:

Assume in CPU1 the following commands are executed:

仅在CPU1中的while和print命令之间添加一个字符而不在CPU0中的A=1和B=1之间添加一个字符以在x86上始终打印1个就足够了吗?

Is it enough to add only lfence between the while and print commands in CPU1 without adding a sfence between A=1 and B=1 in CPU0 to get 1 always printed out on x86?

while (B=0);
lfence
print A

推荐答案

在x86中，所有处理器都以相同的顺序观察单个处理器的写入.无需在示例中进行防护，也无需在x86上的任何常规程序中进行防护.您的程序:

In x86, writes by a single processor are observed in the same order by all processors. No need to fence in your example, nor in any normal program on x86. Your program:

while(B==0);  // wait for B == 1 to become globally observable
print A;      // now, A will always be 1 here

在缓存中确切发生的事情是特定于模型的.各种技巧和推测性行为都可以在缓存中发生，但是 observable 行为始终遵循规则.

What exactly happens in cache is model specific. All kinds of tricks and speculative behavior can occur in cache, but the observable behavior always follows the rules.

请参阅《英特尔系统编程指南第3卷》第8.2.2节.有关内存排序的详细信息.

See Intel System Programming Guide Volume 3 section 8.2.2. for the details on memory ordering.

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