问题描述
我记得在我的体系结构类中假设一次L1缓存命中是1个周期(即与寄存器访问时间相同),但是在现代x86处理器上确实是这样吗?
I remember assuming that an L1 cache hit is 1 cycle (i.e. identical to register access time) in my architecture class, but is that actually true on modern x86 processors?
L1缓存命中需要几个周期?与注册访问相比,它有何不同?
How many cycles does an L1 cache hit take? How does it compare to register access?
推荐答案
关于此主题的一篇很棒的文章:
Here's a great article on the subject:
要回答您的问题-是的,缓存命中的代价与寄存器访问的代价大致相同。当然,未命中缓存的代价也很高;)
To answer your question - yes, a cache hit has approximately the same cost as a register access. And of course a cache miss is quite costly ;)
PS:
具体情况会有所不同,但这链接有一些不错的数字:
The specifics will vary, but this link has some good ballpark figures:
Core i7 Xeon 5500 Series Data Source Latency (approximate)
L1 CACHE hit, ~4 cycles
L2 CACHE hit, ~10 cycles
L3 CACHE hit, line unshared ~40 cycles
L3 CACHE hit, shared line in another core ~65 cycles
L3 CACHE hit, modified in another core ~75 cycles remote
L3 CACHE ~100-300 cycles
Local DRAM ~30 ns (~120 cycles)
Remote DRAM ~100 ns
PPS:
这些数字表示很多较旧,较慢的CPU,但比率基本上保持不变:
These figures represent much older, slower CPUs, but the ratios basically hold:
Level Access Time Typical Size Technology Managed By
----- ----------- ------------ --------- -----------
Registers 1-3 ns ?1 KB Custom CMOS Compiler
Level 1 Cache (on-chip) 2-8 ns 8 KB-128 KB SRAM Hardware
Level 2 Cache (off-chip) 5-12 ns 0.5 MB - 8 MB SRAM Hardware
Main Memory 10-60 ns 64 MB - 1 GB DRAM Operating System
Hard Disk 3M - 10M ns 20 - 100 GB Magnetic Operating System/User
这篇关于L1缓存命中的周期/成本与在x86上注册的周期/成本?的文章就介绍到这了,希望我们推荐的答案对大家有所帮助,也希望大家多多支持!