问题描述
是否有任何这样的处理器，它们有指令绕过特定数据的缓存? 这个问题也有一个答案，表明SSE4.2指令确实绕过了缓存.有人可以启发我吗?
Are there any such processors which have instructions to bypass the cache for a specific data? This question also has an answer which suggests that SSE4.2 instructions do bypass the cache. Can somebody enlighten me on that?
推荐答案
通常，缓存策略由内存管理单元(MMU)控制.对于每个地址范围，都会确定一个缓存策略.这些表由OS管理，并且在系统空间中可用.作为对您可能要问的问题的补充说明，对于具有高速缓存的体系结构，通常有CPU命令可用于同步/无效/刷新高速缓存.但是，与MMU表一样，这些命令也仅在系统空间中可用.
In general, the caching policy is controlled by the Memory Management Unit (MMU). For each address range, a caching policy is decided upon. These tables are managed by the OS and are available in system space.As a sidebar answer to a question that you may have intended to ask, for architectures that have a cache, there are usually CPU commands available for synchronizing/invalidating/flushing the cache. However, much as the MMU tables, these commands are also available only in system space.
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