问题描述
好的，这个问题更多的是讨论.我有一个在VHDL中实现pipelined MIPS处理器的项目.
Okay this question is more of a discussion . I have this project of implementing a pipelined MIPS processor in VHDL .
我完全熟悉流水线的概念，但从未使用VHDL实现它.有什么好的资源可以学习VHDL中pipelined processors的实现.
I am fully acquainted with the concepts of pipelining but I have never implemented it with VHDL . What are some good resources to learn implementation of pipelined processors in VHDL .
我需要抢先一步吗?
推荐答案
有一本书数字设计和计算机体系结构，作者:大卫·哈里斯(David Harris)和莎拉·哈里斯(Sarah Harris).请参阅第7章有关微体系结构. 7.5讨论了使用MIPS处理器模型的流水线. 7.6显示了Verilog和VHDL代码的实现.这是一本教科书，还有第二版，其中配套网站上的HDL示例显然是VHDL和SystemVerilog.通过VHDL代码查看，似乎并没有重点放在流水线寄存器上，而是在构建块上. 7.5中的数字应该有很大帮助，也可以从配套站点上下载.
There's a book Digital Design and Computer Architecture by David Harris and Sarah Harris. See Chapter 7 on Microarchitecture. 7.5 talks about pipelining using a MIPS processor model. 7.6 shows Verilog and VHDL code implementing. It's a textbook and there's a second edition, where the HDL examples from the companion web site are VHDL and SystemVerilog apparently. Looking through the VHDL code there doesn't appear to be emphasis on pipeline registers, rather on building blocks. The figures in 7.5 should be a big help and can be downloaded from the companion site as well.
在opencores网站上，有离子-兼容MIPS(tm)的CPU ::概述，您可以在其中可以下载RHD兼容内核的VHDL模型(注册后).流水线阶段在mips_cpu.vhdl中很明显，其名称以其流水线阶段开头(例如p1_alu_flags).有用于测试模型及其零件的测试平台.有关工具的信息，因此您可以生成在其上运行的软件.
On the opencores website there's the Ion - MIPS(tm) compatible CPU :: Overview, where you can download the VHDL model (after registering) for an R3000 compatible core. The pipeline stages are apparent in mips_cpu.vhdl, with names preceded by their pipeline stage (e.g. p1_alu_flags). There are testbenches for exercising the model and it's parts. There's information on tools so you can generate software to run on it.
那里有GeorgiaTech的ECE 3055a课程(请参阅 EE 3055大纲在2000年，其中有4周专门用于流水线.如果您查看 Lab-2帮助，练习是将流水线添加到VHDL中的RTL模型中.显示了第一阶段.您可以从中获得的好处是，可以将流水线添加到您也可以下载 VHDL综合模型(尝试 MIPSSYN.TAR ).所指的指令模拟器可在以下位置找到: ftp://ftp.cs.wi sc.edu/pub/spim/ .对实验室分配2 的描述也可用的. Google仅提供了有关此方面的线索， A中介绍了MIPS模型用于计算机体系结构实验室的MIPS处理器的VHDL综合模型.主页 ECE 3055计算机体系结构和操作系统J. Hamblen .请参阅首页 32位MIPS VHDL模型以获得一组与Altera工具一起使用的类中使用的文件.包含VHDL源代码.指令模拟器将用于验证.
There's GeorgiaTech's ECE 3055a course (see EE 3055 Outline in 2000 where 4 weeks was devoted to Pipelining. If you look at the Lab-2 Help, the exercise is to add pipelining into an RTL model in VHDL. The first stage is shown. What you can get out of this is that you can add pipelining to a behavior model, implied in the book above, as well. You can download the VHDL Synthesis Models (try MIPSSYN.TAR). The instruction simulator referred to can be found here: Index of ftp://ftp.cs.wisc.edu/pub/spim/. A description of Laboratory Assignment 2 is also available. Google is just full of clues on this and the MIPS model was described in A VHDL Synthesis Model of the MIPS Processor for use in Computer Architecture Laboratories. The Home page ECE 3055 Computer Architecture and Operating Systems J. Hamblen. See The Home page 32-bit MIPS VHDL Model for a set of files used in the class used with Altera tools. Contains the VHDL source code. The instruction simulator would be used in verification.
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