问题描述
RISC-V汇编器中的大多数指令在源操作数之前对目标操作数进行排序，例如:
Most instructions in RISC-V assembler order the destination operand before the source one, e.g.:
li t0, 22 # destination, source
li t1, 1 # destination, source
add t2, t0, t1 # destination, source
但是商店的说明却颠倒了顺序:
But the store instructions have that order reversed:
sb t0, (sp) # source, destination
lw t1, (a0) # destination, source
vlb.v v4, (a1) # destination, source
vsb.v v5, (a2) # source, destination
怎么来?
这种(可以说)非对称汇编程序语法设计的动机是什么?
What is the motivation for this (arguably) asymmetric assembler syntax design?
推荐答案
当涉及到目标和源操作数时，我没有看到RISC-V汇编中真正的矛盾之处:目标操作数-当它是指令编码的一部分时-始终对应于汇编语言中的第一个操作数.
I don't see a real inconsistency in RISC-V assembly when it comes to destination and source operands: The destination operand – when it's part of the instruction encoding – always corresponds to the first operand in the assembly language.
如果我们从以下六种指令格式中的四种中查看以下指令示例:
If we look at the following instruction examples from four of the six different instruction formats:
- R型:
add t0, t1, t2 - I型:
addi t0, t1, 1 - J型:
jal ra, off - U型:
lui t0, 0x12345
- R-type:
add t0, t1, t2 - I-type:
addi t0, t1, 1 - J-type:
jal ra, off - U-type:
lui t0, 0x12345
在上面的汇编指令中，目标操作数是第一个操作数.显然，此目标操作数对应于指令编码中的 目标寄存器 .
In the assembly instructions above, the destination operand is the first operand. Clearly, this destination operand correspond to the destination register in the instruction encoding.
现在，让我们集中讨论存储指令(S型格式).例如，请考虑以下存储指令:
Now, let's focus on the store instructions (S-type format). As an example, consider the following store instruction:
sw t0, 8(sp)
我认为很明显，上面的 t0是源操作数 ，因为存储指令将其内容存储在内存中.
I think it is crystal clear that t0 above is a source operand since the store instruction stores its contents in memory.
我们很容易以为8(sp)是目标操作数.但是，通过仔细查看S型指令格式:
We can be tempted to think that 8(sp) is a destination operand. However, by closely looking at the S-type instruction format:
我们可以说上面的汇编指令中的8(sp)部分实际上不是单个操作数，而是两个，即直接8(即 imm )和源寄存器 sp(即， rs1 ).如果指令可以改为表示(类似于addi ):
We can tell that the 8(sp) part in the assembly instruction above isn't really a single operand but actually two, i.e., the immediate 8 (i.e., imm) and the source register sp (i.e., rs1). If the instruction could be expressed instead like (similar to addi):
sw t0, sp, 8
很明显，该指令需要三个操作数，而不仅仅是两个.
It would become evident that this instruction takes three operands, not just two.
寄存器sp没有被修改，只能被读取；因此，不能将其视为目标寄存器.它也是一个源寄存器，就像t0一样–存储指令将其内容存储在内存中的寄存器. 内存是目标操作数 ，因为它是接收t0内容的地方.
The register sp is not modified, only read; it can't be, therefore, considered a destination register. It is also a source register, just as t0 is – the register whose contents the store instruction stores in memory. Memory is the destination operand since it is what receives the content of t0.
S型指令格式未对目标操作数进行编码.指令编码的是目标操作数上的 寻址信息 .对于sw t0, 8(sp)，目标操作数是存储指令根据sp和8计算的有效地址 指定的位置中存储器中的 word.寄存器sp包含有关内存中该字(即目标操作数)的部分寻址信息.
The S-type instruction format doesn't encode a destination operand. What the instruction does encode is addressing information on the destination operand. For sw t0, 8(sp), the destination operand is the word in memory at the location specified by the effective address that the store instruction calculates from sp and 8. The register sp contains part of that addressing information about that word in memory (i.e., the destination operand).
在RISC-V中，对目标操作数进行编码的汇编指令将此操作数作为第一个操作数.但是，存储指令不会对目标操作数进行编码.它的目标操作数是内存中的一个位置，该位置在内存中的地址是根据指令源操作数的内容计算得出的.
Assembly instructions in RISC-V that encode a destination operand have this operand as the first one. A store instruction, however, doesn't encode a destination operand. Its destination operand is a location in memory, and the address of this location in memory is computed from the contents of the instruction source operands.
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