问题描述
在英特尔架构IA32，像MOVL指令，MOVW不允许都是内存位置操作数。例如，指令MOVL（％eax中），（％EDX）是不允许的。为什么呢？
In Intel architecture IA32, instructions like movl, movw does not allow operands that are both memory locations. For example, instruction movl (%eax), (%edx) is not permitted. Why?
推荐答案
答案涉及的RAM更全面的了解。简单地说，RAM只能在两种状态，读模式或写模式。如果你想在RAM中的一个字节复制到另一个位置，你的必须的有RAM以外的临时存储区域，你从阅读切换到书写。
The answer involves a fuller understanding of RAM. Simply stated, RAM can only be in two states, read mode or write mode. If you wish to copy one byte in ram to another location, you must have a temporary storage area outside of RAM as you switch from read to write.
这当然是可能的体系结构能有这样的RAM到RAM中的指令，但它是一个高层次的指令，在微code会转化到RAM中的数据复制到寄存器，然后回RAM。或者，它可能是可能延长RAM控制器能有这样的临时寄存器的只是的这个拷贝的数据，但它难道不为CPU /硬件交互复杂性的增加提供了多大的好处。
It is certainly possible for the architecture to have such a RAM to RAM instruction, but it would be a high level instruction that in microcode would translate to copying of data from RAM to a register then back to RAM. Alternatively, it could be possible to extend the RAM controller to have such a temporary register just for this copying of data, but it wouldnt provide much of a benefit for the added complexity of CPU/Hardware interaction.
编辑：值得注意的是，最近的进展，如混合内存立方体和高带宽的内存是achitectures其中RAM的拓扑结构变得更像是PCI-E和直接内存到内存现在接送可能的，但是这是由于该技术的支持逻辑，而不是在RAM本身。在CPU架构中，这将是在RAM的巨大的块的形式在时间，如DMA，而不是在一个单一的指令的形式，加在CPU高速缓存行为类似于传统的RAM这样的体系结构不得不抽象它作为按我原来的解释
It is worth noting that recent advancements such as Hybrid Memory Cube and High Bandwidth Memory are achitectures in which the RAM topology has become more like PCI-e and direct RAM to RAM transfers are now possible, but that is due to the support logic for the technologies, not the RAM itself. In the CPU architecture, this would be in the form of huge blocks of RAM at a time, like DMA, and not in the form of a single instruction, plus the CPU cache behaves like traditional RAM so the architecture would have to abstract it as per my original explanation
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