问题描述
我最近了解了行锤攻击.为了进行这种攻击，程序员需要为特定数量的地址刷新CPU的完整缓存层次结构.
I recently learned about the row hammer attack. In order to perform this attack the programmer needs to flush the complete cache hierarchy of a CPU for a specific number of addresses.
我的问题是:为什么在x86中必须 CLFLUSH ?如果所有L *高速缓存均透明地起作用(即不需要显式的高速缓存失效)，那么使用该指令的原因是什么?除此之外:CPU难道不可以推测内存访问模式，从而完全忽略指令吗?
My question is: why is CLFLUSH necessary in x86? What are the reasons for ever using this instruction, if all L* caches act transparently (i.e., no explicit cache invalidation needed)? Besides that: isn't the CPU free to speculate memory access patterns, and thereby ignore the instruction altogether?
推荐答案
我认为主要用例是非易失性DIMM ，尤其是英特尔的Optane DC PM.通常是映射的WB-cacheable ，因此需要显式刷新(或movnt)以确保数据持久存储在非易失性存储中.
I think the main use-case is Non-volatile DIMMs, especially Intel's Optane DC PM. It's normally mapped WB-cacheable so requires explicit flushes (or movnt) to make sure data is persisted to non-volatile storage.
Skylake引入了弱排序的高性能CLFLUSHOPT，因为它对于直接连接到内存层次结构的非易失性存储很有用.刷新缓存可确保将数据写到实际内存中，而不会在CPU中脏掉.
Skylake introduced weakly-ordered higher performance CLFLUSHOPT because it's useful for non-volatile storage hooked up to the memory hierarchy directly. Flushing cache makes sure data is written out to actual memory, not still dirty in the CPU.
另请参见超级用户答案有关Optane DC PM(永久性存储器)的某些链接和背景.它是物理地址空间中的非易失性存储，而不仅仅是具有软件技巧的虚拟地址空间中.
See also this SuperUser answer for some links and background on Optane DC PM (Persistent Memory). It's non-volatile storage in physical address-space, not just in virtual address space with software tricks.
Dan Luu关于clwb和pcommit 的文章很有趣:服用的好处操作系统不影响访问存储，详细介绍了当时英特尔针对clflush/clwb的计划及其内存排序语义.该文档是在英特尔仍计划要求称为pcommit(持久提交)的指令作为该过程的一部分时编写的，但英特尔后来决定删除该指令:弃用PCOMMIT指令(来自Intel)上有一些有趣的信息，说明了原因以及如何在罩.
Dan Luu's article on clwb and pcommit is interesting: the benefits of taking the OS out of the way for access to storage, detailing Intel's plans at that point for clflush / clwb and their memory-ordering semantics. It was written while Intel was still planning to require an instruction called pcommit (persistent commit) as part of this process, but Intel later decided to remove that instruction: Deprecating the PCOMMIT Instruction (from Intel) has some interesting info about why, and how things work under the hood.
如果在x86中仍然可以做到这一点，则对于与设备无关的非缓存一致性DMA也可能很重要. (可能不是；我认为现在所有的DMA都是缓存一致的.)
It potentially also matters for non-cache-coherent DMA to devices, if anything can still do that in x86. (Probably not; I think all DMA is cache-coherent now.)
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