在Verilog Generate语句中递增多个Genvar | Generate语句中递增多个Genvar

本文介绍了在Verilog Generate语句中递增多个Genvar的处理方法，对大家解决问题具有一定的参考价值，需要的朋友们下面随着小编来一起学习吧！

问题描述

我正在尝试在verilog中创建一个多级比较器，但我不知道如何在单个生成循环中增加多个genvar.我正在尝试以下方法:

I'm trying to create a multi-stage comparator in verilog and I can't figure out how to increment multiple genvars in a single generate loop. I'm trying the following:

genvar i,j;
//Level 1
generate
  j=0;
  for (i=0;i<128;i=i+1)
  begin: level1Comp
    assign ci1[i] = minw(tc[j],tc[j+1]);
    j = j+2;
  end
endgenerate

并出现以下错误:

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "encoder.v", 322: token is '='
    j=0;

任何人都知道如何在同一generate语句中增加多个genvar吗?或至少获得同等功能?

Anyone know how to increment multiple genvars in the same generate statement? Or at least get equivalent functionality?

推荐答案

假定ci1的深度是tc的一半，并且您想说ci1[0] = min(tc[0], tc[1])，ci[1] = min(tc[2], tc[3])等，则以下方法应该起作用:

Assuming that ci1 has half the depth of tc and you want, say ci1[0] = min(tc[0], tc[1]), ci[1] = min(tc[2], tc[3]) etc, the following should work:

module st_genvar();

  int ci1 [0:127];
  int tc [0:255];

  function int minw(int i1, int i2);
      if(i1 < i2 )
        minw = i1;
      else
        minw = i2;
  endfunction

  genvar i;
  //Level 1
  generate
      for (i=0;i<128;i=i+1)
        begin: level1Comp
            assign ci1[i] = minw(tc[i*2],tc[i*2+1]);
        end
  endgenerate

endmodule

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