问题描述
出身于软件背景，我仍然很难想到硬件.RTL 语言(VHDL 或 Verilog)中 for 循环的等价物是什么?我想我需要一个寄存器来构建一个计数器，以及一个用于分支的多路复用器，是吗?
Coming from a software background, it is still hard for me to think hardware.What would be the equivalent of a for loop in RTL language (VHDL or Verilog) ? I guess I need one register to build a counter, and a multiplexer for branching, is it ?
推荐答案
首先要意识到 HDL 语言有两个不同的面.
The first thing to realise is that an HDL language has two different faces.
- 您在模拟中看到的那个.
- 合成后的那个.
在模拟中，for 循环与大多数语言中的相同:for 循环中的指令被执行多次.
In simulation the for loop is the same as in most languages: the instructions in the for loop get executed a number of times.
要将循环转换为逻辑(因此用于综合)，第一个要求是在编译时必须知道循环大小.因此，您可以从 0 循环到 a_const.但是你不能从 0 循环到 variable_whos_value_can_change.
To convert the loop into logic (thus for synthesis) the first requirement is that the loop size must be know during compile time. Thus you can loop from 0 to a_const. But you can't loop from 0 to variable_whos_value_can_change.
从那里 for 循环变得简单:重复在 for 循环内实现的任何逻辑.
From there the for loop becomes simple: any logic implemented inside the for loop is repeated.
因此 for (i=0; i 做了 4 个加法器.所有这些都并行运行.
Thus for (i=0; i<4; i=i+1) A[i] = B[i] + C[i] makes 4 adders. All of these operate in parallel.
always @( * )
begin
max = c[0];
for (n=1; n<10; n++)
if (c[n]>max) max = c[n];
end
这构成了一个组合逻辑块，其中输入了 10 个 c 值，并且在输出 max 处等于最大的 c.请注意，不涉及寄存器或时钟.
This makes a block of combinatorial logic in which 10 values of c enter and at the output max equals to the largest c. Note that no registers or clock are involved.
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