Verilog 错误:输出或输入端口“Q"必须连接到结构网络表达式

本文介绍了Verilog 错误:输出或输入端口“Q"必须连接到结构网络表达式的处理方法，对大家解决问题具有一定的参考价值，需要的朋友们下面随着小编来一起学习吧！

问题描述

我每次尝试编译时都会收到错误消息，但不知道为什么.任何人都可以帮忙吗?我是 verilog 的新手.

I keep getting the error everytime i try to compile i'm not sure why. Can anyone help? I'm new to verilog.

module D_FF(Clk, D, Reset_n, Q);

    input D, Clk, Reset_n;
    output Q;
    reg Q;

    lab4_GDL f1(.Clk(~Clk), .D(D), .Q(Qm));

    lab4_GDL f2(.Clk(Clk), .D(Qm), .Q(Q));

    always @(posedge Clk, negedge Reset_n)
    begin
        if (Reset_n == 0)
            Q <= 0;
        else
            Q <= D;

    end
endmodule

这就是问题要求我们做的事情:

This is what the problem was asking us to do:

在这部分中，您将在 AlteraDE2 板上实现一个存储器/寄存器电路.该电路具有以下规格:

In this part, you will implement a memory / register circuit on the AlteraDE2 board. The circuit has the following specifications:

DE2 板上开关 SW15-0 的当前值应始终以十六进制显示在四个七段显示器 HEX3-0 上.这部分电路将是组合逻辑.

The current value of switches SW15-0 on the DE2 board should always be displayed in hexadecimal on the four seven-segment displays HEX3-0. This part of the circuit will be combinational logic.

使用 KEY0 作为低电平有效异步复位和 KEY1 作为时钟输入，您应该能够将 SW15-0 上的值存储在 16 位寄存器中.该寄存器应该是一个 16 位的上升沿触发寄存器，它使用 Altera FPGA 中的嵌入式 D 触发器.您可以实例化 D 触发器或为您的寄存器编写行为 Verilog 模型.该寄存器的内容应始终显示在四个七段显示器 HEX7-4 上.

Using KEY0 as an active-low asynchronous reset and KEY1 as a clock input, you should be able to store the value on SW15-0in a 16-bit register. The register should be a 16-bit positive edge triggered register that uses the embedded D flip-flops in the Altera FPGA.You can either instantiate D flip-flops or write a behavioral Verilog model for your register. The contents of this register should always be displayed on the four seven-segment displays HEX7-4.

编写一个提供必要功能的 Verilog 文件.使用 KEY0 作为低电平有效异步复位，使用 KEY1 作为时钟输入.您应该能够重新使用上次实验中的十六进制到 7 段显示模块.当按下复位键时，HEX7-4 将显示全零.

Write a Verilog file that provides the necessary functionality. Use KEY0 as an active-low asynchronous reset, and use KEY1 as a clock input. You should be able to re-use your hex-to-7 segment display module from the last lab. When reset is pressed HEX7-4 will display all zero's.

这也是它所指的最后一个实验室:

module updown (SW, KEY, LEDR, LEDG, GPIO_0, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);
parameter n=32;     // number of bits in updown counter
input [0:0] SW;     // Updown switch 1=up, 0=down
input [0:0] KEY;    // KEY[1] = Clock, KEY[0] = Reset_n
input [0:0] GPIO_0;
output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
output [n-1:0] LEDR;    // Display binary count (active high) on Red LEDs
output [1:0] LEDG;  // Display Clock on LEDG[1], Reset_n on LEDG[0]
wire Clock, Reset_n, Updown;
reg [n-1:0] Count;

assign Clock = GPIO_0[0];
assign Reset_n = KEY[0];
assign Updown = SW[0];
assign LEDR = Count;
assign LEDG[1:0] = {Clock, Reset_n};

always @(posedge Clk, negedge Reset_n) //clock = Clk
    if (Reset_n == 0)       // active-low asynchronous reset
        Q <= 0;
    else
        Q <= D;

我的 lab4_GDL 如下:

// A gated RS latch
module lab4_GDL(Clk, D, Q);
    input Clk, D;
    output Q;

    wire R_g, S_g, Qa, Qb /* synthesis keep */;
    assign R = ~D;
    assign R_g = ~(R & Clk);
    assign S_g = ~(D & Clk);
    assign Qb = ~(R_g & Qa);
    assign Qa = ~(S_g & Qb);

    assign Q = Qa;

endmodule

输出或输入端口

Verilog 错误:输出或输入端口“Q"必须连接到结构网络表达式

问题描述

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