Verilog 编译错误:意外的“["，期待“IDENTIFIER"；或“TYPE_IDENTIFIER"或 '#' 或 '('

问题描述

我想设计一个带有生成结构和二维内存的简单乘法器.但我无法编译以下 verilog 代码.谁能给点提示?

I want to design a simple multiplier with the generate construct and two dimensional memory. But I can not compile the following verilog code. Could anyone give some hint please?

module classic_multiplier(
    a, b,
    a_by_b);
parameter M = 2;

input [M-1:0] a, b;
output reg [M-1:0] a_by_b [0:2*M-2];

//the first and
genvar i, k;
generate begin
    for(k = 0; k <= M-1; k=k+1) begin
        for(i = 0; i <= k; i=i+1) begin
            a_by_b[k][i] = a[i] & b[k-i];
        end
    end
end
endgenerate
endmodule

推荐答案

这里的问题似乎是您有一个 2D 输出端口 (a_by_b).我不太确定你为什么需要它作为乘法器，输出端口大小应该是 2*M，所以:

It seems the problem here is that you have a 2D output port (a_by_b). I'm not quite sure why you would need it for a multiplier anyway, the output port size should be 2*M, so:

output reg [(2*M-1):0] a_by_b;

此外，在 generate 之后不需要 begin(因此也不需要匹配的 end)，但是好的，这不是真正的问题，您可以根据需要添加它们.

Also, there is no need for the begin after generate (and thus no need either for the matching end), but ok, that's not really the problem here, you can add them if you want.

接下来，需要命名generate块内的for循环，例如:

Next, for loops inside a generate block need to be named, for example:

generate
  for(k = 0; k <= M-1; k=k+1) begin : for_outer
    for(i = 0; i <= k; i=i+1) begin : for_inner
      a_by_b[k][i] = a[i] & b[k-i];
    end
  end
endgenerate

当然，如果您更改了a_by_b 的定义，则需要更改for 循环内的代码.

Of course, you will need to change the code inside the for loops if you change the definition of a_by_b.

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