将参数传递给Verilog模块

问题描述

我正在为FPGA设计编写一些Verilog模块.我环顾互联网，以了解如何最好地参数化我的模块.我看到经常出现两种不同的方法.我在下面提供了两种不同方法的示例.以下哪种方法是对模块进行参数设置的最佳方法?有什么区别?是否依赖于供应商(Altera与Xilinx)?

I am in the process of writing some Verilog modules for an FPGA design. I looked around the internet to find out how I best parametrize my modules. I see two different methods occurring often. I included an example hereunder of the two different methodologies.Which of these methods is the best way to parametrize modules?What is the difference?Is it vendor-dependent (Altera vs Xilinx)?

第一种方法:模块定义:

The first method:Module definition:

module busSlave #(parameter DATA_WIDTH = 1) (
  input [DATA_WIDTH-1:0] bus_data,
  input                  bus_wr,
  ...
);
endmodule

模块实例化:

module top;

  //DATA_WIDTH is 32 in this instance
  busSlave #(.DATA_WIDTH(32)) slave32(
    .bus_data(data_0),
    .bus_wr(wr_0),
    ...
    );

  //DATA_WIDTH is 64 in this instance
  busSlave #(.DATA_WIDTH(64)) slave64(
    .bus_data(data_1),
    .bus_wr(wr_1),
    ...
    );
endmodule

第二种方法:模块定义:

The second method:Module definition:

module busSlave(
  parameter DATA_WIDTH = 1;
  input [DATA_WIDTH-1:0] bus_data,
  input                  bus_wr,
  ...
);
endmodule

模块实例化:

module top;

  //DATA_WIDTH is 32 in this instance
  busSlave slave32(
    .bus_data(data_0),
    .bus_wr(wr_0),
    ...
    );
  defparam slave32.DATA_WIDTH = 32;

  //DATA_WIDTH is 64 in this instance
  busSlave slave64(
    .bus_data(data_1),
    .bus_wr(wr_1),
    ...
    );
  defparam slave32.DATA_WIDTH = 64;
endmodule

预先感谢

示例中的一些更正

推荐答案

已计划弃用defparam语句. IEEE Std 1800-2012，附件C(不推荐使用)的"C.4.1 Defparam语句"部分指出:

The defparam statement is scheduled for deprecation. The IEEE Std 1800-2012, Annex C (Deprecation), section "C.4.1 Defparam statements" states:

Verilog的许多功能都取决于供应商.

Many features of Verilog are vendor-dependent.

这篇关于将参数传递给Verilog模块的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持！