Verilog 中的分配/取消分配需要什么?

问题描述

我在这里给出了 2 个 Verilog 模块，它们在模拟过程中表现相同.但是我不明白为什么在这些模块中使用 assign/deassign ，即这两个代码之间有什么区别?

I am here giving here 2 Verilog modules, which during simulation behaves same. But I don't understand that why to use assign/deassign in these modules, i.e. what is the difference between these 2 codes?

// Code 1 - Without assign-deassign
module dff (q,qbar,clk,reset,d)
  input clk, reset, d;
  output reg q, qbar;

  always @ (posedge reset, negedge clk)
  begin
    if(reset)
    begin
      q=1;
      qbar=0;
    end
    else
    begin
      q=d;
      qbar=~d;
    end
  end
endmodule

// Code 2 - With assign-deassign
module dff (q,qbar,clk,reset,d)
  input clk, reset, d;
  output reg q, qbar;

  always @ (negedge clk)
  begin
    q=d;
    qbar=~d;
  end

  always @ (reset)
  begin
    if(reset)
    begin
      assign q=1;
      assign qbar=0;
    end
    else
    begin
      deassign q;
      deassign qbar;
    end
  end
endmodule

推荐答案

在您的示例中，过程分配/取消分配语句的最初目的是在两个不同的进程中将同步逻辑与异步逻辑分开.由于同步模块不必在每个时钟周期检查复位信号，因此仿真效率也更高.对锁存器建模也更有效地进行仿真，因为您不必在每次数据更改时检查使能信号，只有在锁存器打开时才检查.

The original purpose of the procedural assign/deassign statements in your example was to separate synchronous logic from asynchronous logic in two distinct processes. It's also more efficient for simulation because the synchronous block does not have to check the reset signal every clock cycle. Modeling latches is also more efficient for simulation because because you don't have to check the enable signal every time the data changes, only when the latch is open.

早期的综合工具可以综合这种结构，但不幸的是，大综合供应商决定不支持它，所以没有人再使用这些程序结构.

This construct was synthesizable by early synthesis tools, but unfortunately, the big synthesis vendor decided not to support it, so no one uses these procedural constructs anymore.

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