问题描述
$大小之间的区别是什么和 $位运营商的Verilog？
如果说我的变量， [9：0] A ， [6：0] b ， [31：0]ç
What is the difference between $size and $bits operator in verilog.?if I've variables, [9:0]a,[6:0]b,[31:0]c.
c <= [($size(a)+$size(b)-1]-:$bits(b)];
将在什么'C'的输出从上述前pression？
What will be the output at 'c' from the above expression?
推荐答案
$大小应返回维度，相当于元素的个数为 $高 - 低$ + 1 。它是相对于该维度，不仅位计数。如果类型是一维数组包装或整数类型，它等于 $位。
$size shall return the number of elements in the dimension, which is equivalent to $high - $low + 1. It is relative to the dimension, not only bit counts. If the type is 1D packed array or integral type, it is equal to $bits.
$位系统函数返回到举行前pression为比特流所需的比特数。
$bits system function returns the number of bits required to hold an expression as a bit stream.
$bits ( [expression|type_identifier] )
在具有动态大小的类型，它目前是空称之为返回0。这是直接与动态大小类型标识符使用 $位系统功能的错误。
It returns 0 when called with a dynamically sized type that is currently empty. It is an error to use the $bits system function directly with a dynamically sized type identifier.
我不知道你的问题， C＆LT; = [（$大小（A）+ $尺寸（B）-1] - ：$位（B）; 它是在RHS一个有效的前pression你谈论的阵列范围前pression， [N +：M] 或 [N - ：M]？
I have no idea about your question, c <= [($size(a)+$size(b)-1]-:$bits(b)];. Is it a valid expression in RHS? Are you talking about the array range expression, [n +: m] or [n -: m] ?
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