哪些x86指令需要两个(或更多)内存操作数?

问题描述

我认为那里是零.但是，我在这里看到

I thought that there was zero. But, I see here,

我找不到任何能解释什么指令的资料，尽管很少见.有什么例外?

I can't find anything that explains what instructions, though rare, exist. What are the exceptions?

推荐答案

x86指令最多可以具有一个ModR/M + SIB + disp0/8/32.因此，零指令具有两个显式内存操作数.

An x86 instruction can have at most one ModR/M + SIB + disp0/8/32. So there are zero instructions with two explicit memory operands.

x86存储器指令全部具有至少一个隐式存储器操作数，其位置被烘焙到操作码中，例如访问堆栈的push或字符串指令movs和cmps.

The x86 memory-memory instructions all have at least one implicit memory operand whose location is baked in to the opcode, like push which accesses the stack, or the string instructions movs and cmps.

我将使用[mem]指示ModR/M寻址模式，该模式可以是[rdi]，[RIP+whatever]，[ebx+eax*4+1234]或您喜欢的任何内容.

I'll use [mem] to indicate a ModR/M addressing mode which can be [rdi], [RIP+whatever], [ebx+eax*4+1234], or whatever you like.

• push [mem]:读取[mem]，写入隐式[rsp](在更新rsp之后).
• pop [mem]
• call [mem]:从[mem]读取新的RIP，将返回地址压入堆栈.
• movsb/w/d/q :读取DS:(E)SI，写入ES:(E)DI(或在64位模式RSI和RDI中).两者都是隐式的；只有DS段reg是可重写的.可用于rep.

• cmpsb/w/d/q :读取DS:(E)SI和ES:(E)DI(或在64位模式RSI和RDI中).两者都是隐式的；只有DS段reg是可重写的.可用于repe/repne.

• push [mem]: reads [mem], writes implicit [rsp] (after updating rsp).
• pop [mem]
• call [mem]: reads a new RIP from [mem], pushes a return address on the stack.
• movsb/w/d/q: reads DS:(E)SI, writes ES:(E)DI (or in 64-bit mode RSI and RDI). Both are implicit; only the DS segment reg is overridable. Usable with rep.

• cmpsb/w/d/q: reads DS:(E)SI and ES:(E)DI (or in 64-bit mode RSI and RDI). Both are implicit; only the DS segment reg is overridable. Usable with repe / repne.

MPX bndstx mib, bnd :将边界存储在bnd和指针中将mib的索引寄存器中的值转换为绑定表条目(BTE)，并使用mib的基地址进行地址转换." 操作"部分显示了负载和存储，但是我对MPX不够了解.

MPX bndstx mib, bnd: "Store the bounds in bnd and the pointer value in the index register of mib to a bound table entry (BTE) with address translation using the base of mib." The Operation section shows a load and a store, but I don't know enough about MPX to grok it.

movdir64b r16/r32/r64, m512 .有自己的功能，即将在中提供Tremont (Goldmont Plus Atom的前身).将具有64字节写入原子性的64字节直接存储(WC)移动到源存储器地址到目标存储器地址.目标操作数是ModRM中的(对齐原子)es: /r，源操作数是ModRM中的/m(非对齐非原子).

movdir64b r16/r32/r64, m512. Has its own feature bit, available in upcoming Tremont (successor to Goldmont Plus Atom). Moves 64-bytes as direct-store (WC) with 64-byte write atomicity from source memory address to destination memory address. Destination operand is (aligned atomic) es: /r from ModRM, source is (unaligned non-atomic) the /m from ModRM.

对存储使用写合并，请参见描述.这是x86 CPU供应商第一次保证原子性超出lock cmpxchg16b的8个字节.但是不幸的是，它实际上并不适合多线程，因为它会强制执行类似NT的缓存逐出/旁路行为，因此其他内核将不得不从DRAM而不是共享的外部缓存中读取它.

Uses write-combining for the store, see the description. It's the first time any x86 CPU vendor has guaranteed atomicity wider than 8 bytes outside of lock cmpxchg16b. But unfortunately it's not actually great for multithreading because it forces NT-like cache eviction/bypass behaviour, so other cores will have to read it from DRAM instead of a shared outer cache.

AVX2收集和AVX512分散指令值得商bat.它们显然会进行多次加载/存储，但是所有指针都来自一个SIMD向量(和标量基数).

AVX2 gather and AVX512 scatter instructions are debatable. They obviously do multiple loads / stores, but all the pointers come from one SIMD vector (and a scalar base).

我没有计算pusha，fldenv， xsaveopt ，iret或enter的嵌套级别> 1，可以多次存储或加载到一个连续的块中.

I'm not counting instructions like pusha, fldenv, xsaveopt, iret, or enter with nesting level > 1 that do multiple stores or loads to a contiguous block.

我也不计算ins/outs字符串指令，因为它们将内存复制到I/O空间或从I/O空间复制. I/O空间不是内存.

I'm also not counting the ins / outs string instructions, because they copy memory to/from I/O space. I/O space isn't memory.

我没有在 http://felixcloutier.com/x86/上查看VMX或SGX指令index.html ，只是主列表.我不认为我没有错过任何比赛，但我当然可以.

I didn't look at VMX or SGX instructions on http://felixcloutier.com/x86/index.html, just the main list. I don't think I missed any, but I certainly could have.

这篇关于哪些x86指令需要两个(或更多)内存操作数?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持！