问题描述
module counter (clk,rst,enable,count);
input clk, rst, enable;
output [3:0] count;
reg [3:0] count;
always @ (posedge clk or posedge rst)
if (rst) begin
count <= 0;
end else begin : COUNT
while (enable) begin
count <= count + 1;
disable COUNT;
end
end
endmodule
(来源:http://www.asic-world.com/verilog/verilog_one_day2.html#While)
据我所知，<= 是一个关系运算符，如果为真，它将返回 1，如果为假，它将返回 0，但它在这段代码中的何处返回?
From what I have learnt, <= is a relational operator and it will return 1 if true and 0 if false, but where does it return in this code?
推荐答案
在您的代码上下文中，<= 不是关系运算符，而是 赋值运算符.Verilog 中有两种类型的赋值:
In the context of your code, <= is not a relational operator, it is an assignment operator. There are two types of assignment in Verilog:
阻塞:
=
非阻塞:
在 Verilog 设计中，您
In a Verilog design, you
总是为组合逻辑使用阻塞赋值
对于顺序逻辑
如果不这样做，您的模拟将不确定 - 每次运行时它的行为不一定相同.这当然不好.
If you do not, you simulation will be indeterminate - it will not necessarily behave the same way every time you run it. Which, of course, is not good.
那么，这是为什么呢?好吧，首先你必须知道 Verilog 有 4 个调度区域:
So, why is that? Well, to start you must learn that Verilog has 4 scheduling regions:
from prev time step
|
ACTIVE
|
INACTIVE
|
NBA
|
POSTPONED
|
V
to next time step
阻塞分配在 ACTIVE 区域中执行.然而，虽然在 ACTIVE 区域中评估非阻塞分配的右侧，但分配直到 NBA 区域才会发生.这就是为什么需要将它们用于时序逻辑的关键.
Blocking assignments are executed in the ACTIVE region. However, while the right-hand side of a non-blocking assignment is evaluated in the ACTIVE region, the assignment does not occur until the NBA region. This is key to why you need to use them for sequential logic.
那么，为什么需要对时序逻辑使用非阻塞赋值?原因是因为右侧的评估和左侧的分配之间的延迟使得 Verilog 模拟能够确定，即每次运行时都以相同的方式运行.这种延迟意味着模拟的行为不依赖于 always 块的执行顺序，如果只使用阻塞赋值的话.
So, why do you need to use non-blocking assignments for sequential logic? The reason is because the delay between evaluation of the right-hand side and assignment of the left hand side enables a Verilog simulation to be determinate, ie to behave the same way every time you run it. This delay means that the behaviour of the simulation does not depend on the order in which the always blocks are executed, which it would if only blocking assignments were used.
对评估非阻塞赋值的右侧和赋值左侧之间的延迟的一个简单类比是实际触发器的clock-to-Q延迟.在真正的触发器中，被采样的 D 输入(通过时钟)和被驱动的 Q 输出之间总是有一个小的延迟(时钟到 Q 的延迟).这对于真实时序逻辑的正确操作至关重要.例如，如果在一个真正的触发器中没有时钟到 Q 的延迟，而不是在 4 级移位寄存器中第一个触发器的 D 输入正好需要 4 个时钟才能到达 Q 输出第四个触发器，它可以使用 1 到 4 之间的任意数量的时钟:它的行为也是不确定的.
A simple analogy to the delay between evaluating the right-hand side of a non-blocking assignment and assigning the left-hand side is the clock-to-Q delay of a real flip-flop. In a real flip-flop, there is always a small delay (clock-to-Q delay) between the D input being sampled (by the clock) and the Q output being driven. This is vital to the correct operation of real sequential logic. For example, if there were no clock-to-Q delay in a real flip-flop instead of it taking exactly 4 clocks for the D input of the first flip-flop in a 4-stage shift register to get to the Q output of the fourth flip-flop, it could take any number of clocks between 1 and 4: its behaviour would also be indeterminate.
这篇关于<= 运算符在这段代码中做了什么?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持！