我可以在makefile目标中有多个％的符号吗?

问题描述

所以我有一个具有目标依赖项的makefile:

So I have a makefile with a target dependency like this:

all: $(foreach lang, $(LANGS), $(foreach models,$(MODELS),targetName$(model).xml$(lang)))

和targetName目标看起来像这样:

and the targetName target looks like this:

targetName%.xml%: MODEL\=% targetName.xml*

但是它不起作用.我收到此错误:

But it doesn't work. I get this error:

make[1]: *** No rule to make target `targetNameMYMODEL.xmlen', needed by `all'.  Stop.

但是，在目标名称目标中使用硬编码语言调用全部"是这样的:

however, calling 'all' with a hardcoded language in the targetName target like this works:

all: $(foreach lang, $(LANGS), $(foreach models,$(MODELS),targetName$(model).xmlen))

并在不使用all或targetName语言的情况下调用'all'也可以正常工作.我在想，也许Makefile不喜欢目标名称中有两个百分号.

and calling 'all' without the language in either all or targetName works fine as well. I'm thinking perhaps Makefile doesn't like having two percent signs in the target name.

而且，由于我有点继承了这个makefile，因此有人可以告诉我MODEL \ =％是什么意思吗?还有一个类似的目标:MODEL%: ;，但我不确定\ =％的含义.

Also, since I sort of inherited this makefile, can someone tell me what that MODEL\=% means? There is another target that looks like this: MODEL%: ; but i'm not sure what the \=% means.

因此，根据此响应进一步说明:

So to clarify further based on this reponse:

我有一个清单，例如5种模型和一份清单，例如5种语言，目标是生成25个文件，每种语言和模型的组合一个.

I have a list of, say, 5 Models and a list of say 5 Languages, the goal is to generate 25 files, one for each combination of languages and models.

targetName％.xml target最初将建立一个名为targetName.xml的文件，但现在我需要它来构建诸如targetName.xml之类的文件.这就是为什么我需要两个％符号的原因.

targetName%.xml target would originally build a file called targetName.xml but now I need it to build something like targetName.xml That's why I needed the two % signs.

我正在使用嵌套的foreach遍历这两个列表，但是我很难将这些变量传递给目标.我尝试从foreach语句中导出语言变量，并尝试将targetName％.xml的内容放入for循环中以遍历那里的语言.后者不起作用，因为在循环的执行"部分有Makefile命令(例如eval).

I'm cycling through these two lists with a nested foreach as shown above, but I'm having a hard time passing those variables around to targets. I've tried exporting the language variable from the foreach statement, I've tried putting the contents of the targetName%.xml in a for loop to loop through the languages there. The latter doesn't work because there are Makefile commands (like eval for example) in the 'do' portion of the loop.

推荐答案

您是对的，Make不喜欢目标名称中的两个%符号.那只是Make的通配符处理并非所有人都希望的方式之一.有一种方法可以自动生成对一个变量的值进行迭代的所有模式规则(对另一个变量使用%).有点丑陋，但是如果您要那样，我们可以告诉您.

You're right, Make doesn't like two % symbols in the target name. That's just one of the ways in which Make's wildcard handling isn't all one might wish for. There is a way to generate all of the pattern rules iterating over the values of one variable (and using % for the other) automatically; it's a little ugly, but if that's what you want we can show you.

但这行很乱:

targetName%.xml%: MODEL\=% targetName.xml*

除了目标中有两个通配符的问题外，最后一个前置词targetName.xml*的确切含义是:一个名为targetName.xml*的目标(或文件).星号不会展开，也不会扩展到以targetName.xml开头的所有现有文件或其他任何文件的列表.

Apart from the problem of two wildcards in the target, the last preq, targetName.xml* will mean exactly that: a target (or file) called targetName.xml*. The asterisk will not be expanded, not to a list of all existing files that start with targetName.xml, or anything else.

然后是MODEL\=%，这表明该makefile的作者有些困惑(并且不相信测试).如果通配符的值为foo，则这将指示一个前提条件，该前提条件是名为MODEL=foo的目标(或文件). \转义" =，以使Make不会中止，但这只是抑制了正常的错误消息.我认为作者的想法是这样的:

Then there's MODEL\=%, which indicates that the author of this makefile was a little confused (and didn't believe in testing). If the value of the wildcard is foo, then this will indicate a prerequisite which is a target (or file) named MODEL=foo. The \ "escapes" the =, so that Make will not abort, but that is simply suppression of a healthy error message. I think what the author had in mind was something like this:

targetName%.xml: MODEL=%

targetName%.xml: $(wildcard targetName.xml*)
    do some things

第一个规则不是指定先决条件，而是设置目标特定的变量.因此，当Make尝试通过doing some things构建targetNamefoo.xml时，变量MODEL在该命令的上下文中将具有值foo.第二条规则有一个由wildcard生成的优先列表.您不能在一行中混合使用特定于目标的变量和前提条件.

The first rule is not specifying a prerequisite, it is setting a target-specific variable. So when Make tries to build targetNamefoo.xml by doing some things, the variable MODEL will have the value foo in the context of that command. The second rule has a preq list, generated by wildcard; you can't mix target-specific variables and preqs in one line.

我们可以提供进一步的建议，但是如果我们可以更清楚地了解您正在尝试做什么，那将有所帮助.

We can give further advice, but it would help if we could see a little more clearly what you're trying to do.

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