问题描述
我在如何制作时钟分频器中找到了这段代码。我对如何使用计数器做一个除法器有一个大致的了解，但是我不确定这段代码在做什么以及为什么这样做。
实体clkdiv是
端口（mclk：在STD_LOGIC中;
clr：在STD_LOGIC中;
clk190：在STD_LOGIC中;
clk48：在STD_LOGIC中）;
end clkdiv;
clkdiv的clkdiv架构是
signal q：std_logic_vector（23 downto 0）;
开始
-时钟分频器
process（mclk，clr）如果clr ='1'，则
开始
然后
q elsif mclk'event and mclk ='1'然后
q< = q + 1;
结尾，如果；
结束程序；
clk48< = q（19）;
clk190< = q（17）;
end clkdiv;我知道该示例基于2板，输入时钟为50MHz。该代码应创建48hz时钟信号和190hz时钟信号。 解决方案 50MHz / 48Hz = 104166.7，所以您无法准确到达那里。
如果您使用的计数器在50MHz时可计数到104167，那么您将获得接近48 Hz（47.9999846 Hz的脉冲），对于大多数用途来说可能已经足够了。
不要将计数器的输出用作时钟，而是在绕回时钟时使用单个脉冲作为时钟使能-这样您可以获得更好的结果。整个设计过程中只有一个时钟并启用了各个部分，即可实现。
I found this code in how to make a clock divider. I have a general understanding on how to make a divider using counters but i not sure what this code is doing and why its doing it.
entity clkdiv is
Port ( mclk : in STD_LOGIC;
clr : in STD_LOGIC;
clk190 : out STD_LOGIC;
clk48 : out STD_LOGIC);
end clkdiv;
architecture clkdiv of clkdiv is
signal q: std_logic_vector(23 downto 0);
begin
--clock divider
process(mclk,clr)
begin
if clr ='1' then
q <= X"000000";
elsif mclk'event and mclk = '1' then
q <= q+1;
end if;
end process;
clk48 <= q(19);
clk190 <= q(17);
end clkdiv;
I know that the example is on the basis 2 board, the input clock is 50MHz. This code is supposed to create a 48hz clock signal and 190hz clock signal.
解决方案 50MHz/48Hz = 104166.7, so you can't get there exactly.
If you use a counter which counts up to 104167 at 50MHz, you'll get a single pulse at close to 48 Hz (47.9999846 Hz - which is probably good enough for most purposes).
Don't use the output of the counter as a clock, use a single pulse when it wraps around as a clock enable - you get much better results that way. A single clock throughout the design with enabled sections is the way to do it.
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