问题描述
当试图从I / O端口在x86阅读（特别是奔腾），可在家庭中的指令阻塞在等待数据或将他们总是立即返回？
When trying to read from I/O ports on x86 (Pentium specifically), can the IN family of instructions block while waiting for data or will they always return immediately?
推荐答案
简短的回答：是，从理论上讲，一个I / O设备的可能的导致CPU块上的I / O读取（在指令）。
Short answer: Yes, in theory, an I/O device could cause the CPU to "block" on an I/O read (in instruction).
不过，我不知道有任何内存或实际停滞任何时间段显著I / O设备，造成CPU执行，以块。
However, I'm not aware of any memory or I/O devices that actually stalled for any significant period of time, causing CPU execution to "block".
龙答：
的在和退出的指令执行I / O读/写，这几乎等同于一个典型存储器总线周期。唯一的区别是将不同的信号（多个）被断言，以指示I / O与存储器存取
The in and out instructions perform an I/O read/write, which is almost identical to a typical memory bus cycle. The only difference is that a different signal(s) is asserted to indicate I/O vs. memory access.
现在这得到pretty低层次，细节得到与后来的CPU更加复杂。我引用去到有关在x86总线周期信号电平的细节，从8086/8088。
Now this gets pretty low-level, and the details get more complex with later CPUs. I'm referencing this presentation goes into signal-level detail about the x86 bus cycles, starting with the 8086/8088.
8086/8088读周期1等待状态
我们在这里看到，有一个就绪信号，这是由内存或I / O设备断言，以表明它已经presented其数据公交车，是的就绪的为CPU锁定它，这PDF州
We see here that there is a READY signal, which is asserted by the memory or I/O device, to indicate that it has presented its data to the bus, and is ready for the CPU to latch it in. That PDF states
86对控制总线
- 就绪输入选中T3在
– READY Input "Checked" During T3
- 如果READY无效（LOW），附加T3国加入
– If READY is Inactive (LOW), Additional T3 States are Added
- 这些附加的T3国被称为等待状态
– These Additional T3 States are Called "Wait States"
因此，它是可能的，至少这些旧的CPU，一个设备可以就绪，之前声称等待多个周期上的内存导致CPU为块或I / O指令。
So it is possible, with these older CPUs at least, that a device could wait many cycles before asserting READY, causing the CPU to "block" on the memory or I/O instruction.
我相信这仍然是有效的，至少要经过和，该传达给北桥/南桥（或的）设置。这些器件然后在内存/ IO请求适当的设备迈进。有了这个设置，我怀疑PCH将允许传出的I / O读来搪塞通过QPI链路的处理器的要求。
Now days, the architecture is much different. Modern x86 processors don't even have "address" and "data" pins per se, but instead have links like DMI and QPI, which communicate to a northbridge/southbridge (or Platform Controller Hub) setup. These devices then forward on the memory/IO requests to appropriate devices. With this setup, I doubt that the PCH would allow an outgoing I/O read to stall a processor request over the QPI link.
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