问题描述
由于
some_atomic.load（的std :: memory_order_acquire）不只是下降到通过
一个简单的加载指令，和
some_atomic.store（的std :: memory_order_release）下降到通过一个简单的
存储指令。
据了解，在 86 作为操作负荷（）和存储（）内存屏障 memory_order_consume，memory_order_acquire，memory_order_release，memory_order_acq_rel 不需要处理器指令。
It is known that on x86 for the operations load() and store() memory barriers memory_order_consume, memory_order_acquire, memory_order_release, memory_order_acq_rel does not require a processor instructions.
但在 ：我们知道，在这里都为装载内存屏障（）和存储（）：
http://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-2012-Herb-Sutter-atomic-Weapons-1-of-2
http://channel9.msdn.com/Shows/Going+Deep/Cpp-and-Beyond-2012-Herb-Sutter-atomic-Weapons-2-of-2
关于CPU的不同的架构：
About different architectures of CPUs: http://g.oswego.edu/dl/jmm/cookbook.html
其次，但在 86 ，这两条线有不同的记忆障碍是在拆卸code相同的（ MSVS2012 x86_64的）的CAS操作：
Next, but for the CAS-operation on x86, these two lines with different memory barriers are identical in Disassembly code (MSVS2012 x86_64):
a.compare_exchange_weak(temp, 4, std::memory_order_seq_cst, std::memory_order_seq_cst);
000000013FE71A2D mov ebx,dword ptr [temp]
000000013FE71A31 mov eax,ebx
000000013FE71A33 mov ecx,4
000000013FE71A38 lock cmpxchg dword ptr [temp],ecx
a.compare_exchange_weak(temp, 5, std::memory_order_relaxed, std::memory_order_relaxed);
000000013FE71A4D mov ecx,5
000000013FE71A52 mov eax,ebx
000000013FE71A54 lock cmpxchg dword ptr [temp],ecx
拆卸code。通过 GCC 4.8.1编译的x86_64 - GDB
a.compare_exchange_weak(temp, 4, std::memory_order_seq_cst, std::memory_order_seq_cst);
a.compare_exchange_weak(temp, 5, std::memory_order_relaxed, std::memory_order_relaxed);
0x4613b7 <+0x0027> mov 0x2c(%rsp),%eax
0x4613bb <+0x002b> mov $0x4,%edx
0x4613c0 <+0x0030> lock cmpxchg %edx,0x20(%rsp)
0x4613c6 <+0x0036> mov %eax,0x2c(%rsp)
0x4613ca <+0x003a> lock cmpxchg %edx,0x20(%rsp)
是在x86 / x86_64的平台，任何原子CAS-操作，比如像这样的 atomic_val.compare_exchange_weak（温度，1日的std :: memory_order_relaxed，性病:: memory_order_relaxed）的例子; 总是满意的订货的std :: memory_order_seq_cst ？
如果在x86上的任何CAS操作总是顺序一致性（的std :: memory_order_seq_cst ）无论障碍跑，然后在ARMv8是一样的吗？
And if the any CAS operation on the x86 always run with sequential consistency (std::memory_order_seq_cst) regardless of barriers, then on the ARMv8 it is the same?
问：应的std :: memory_order_relaxed 为 CAS 的顺序块存储器在x86或ARM巴士？
QUESTION: Should the order of std::memory_order_relaxed for CAS block memory bus on x86 or ARM?
答：在 86任 compare_exchange_weak（） 任何操作的std :: memory_orders （甚至的std :: memory_order_relaxed ）始终将转换为 LOCK CMPXCHG ，并有等于昂贵 XCHG - 昂贵。
ANSWER: On x86 any compare_exchange_weak() operations with any std::memory_orders(even std::memory_order_relaxed) always translates to the LOCK CMPXCHG with lock bus, to be really atomic, and have equal expensive to XCHG - "the cmpxchg is just as expensive as the xchg instruction".
（安此外： XCHG 等于 LOCK XCHG ，但 CMPXCHG 不等于 LOCK CMPXCHG （这实在是原子）
(An addition: XCHG equal to LOCK XCHG, but CMPXCHG doesn't equal to LOCK CMPXCHG(which is really atomic)
在 ARM和PowerPC的any`compare_exchange_weak（）作为不同的std :: memory_orders有有型动物锁的处理器指令，通过的。
On ARM and PowerPC for any`compare_exchange_weak() for different std::memory_orders there are differents lock's processor instructions, through LL/SC.
处理器内存屏障指令：的
Processor memory-barriers-instructions for x86(except CAS), ARM and PowerPC: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
推荐答案
您不应该担心什么指示编译器映射一个给定的C11构建为这不捕捉一切。相反，你需要开发code相对于C11的内存模型的保证。由于上述评论的笔记，你的编译器或将来的编译器是免费的，只要它不违反C11的内存模型来重新排序轻松内存操作。这也是一个值得通过像CDSChecker一个工具来查看内存模式下，允许哪些行为你运行code。
You shouldn't worry about what instructions the compiler maps a given C11 construct to as this doesn't capture everything. Instead you need to develop code with respect to the guarantees of the C11 memory model. As the above comment notes, your compiler or future compilers are free to reorder relaxed memory operations as long as it doesn't violate the C11 memory model. It is also a worthwhile running your code through a tool like CDSChecker to see what behaviors are allowed under the memory model.
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