在SIGILL的Andr​​oid NDK code

问题描述

我有一个NDK应用程序在市场上，并得到有关 SIGILL 信号本地崩溃报告。 （我用谷歌breakpad生成本地崩溃报告。）下面是详细信息：

I have an NDK app out on market and got a native crash report about a SIGILL signal. (I use google breakpad to generate native crash reports.) Here are the details:

• 在我的应用程序被编译为 armeabi-V7A ，与 NEON支持。
• 在它坠毁在了NVIDIA的Tegra 2处理器，它是ARM-7（的Cortex-A9）。
• 在它发生的每一次。 （联系用户）
• 在失事地址在 0x399cc ，该信号是 SIGILL ，这是在我的code。

• My app is compiled for armeabi-v7a, with NEON support.
• It crashed on a NVIDIA Tegra 2 Processor, which is ARM-7 (Cortex-A9).
• It happens every time. (contacted the user)
• The crash address was at 0x399cc, the signal was SIGILL, and it's in my code.

寄存器和拆卸：

 r4 = 0x001d50f0    r5 = 0x001d50f0    r6 = 0x598e2a3c    r7 = 0x00000000
 r8 = 0x00000001    r9 = 0x001c22b0   r10 = 0x00000000    fp = 0x81216264
 sp = 0x598e2a18    lr = 0x816399cb    pc = 0x816399cc

0x000399c6 <_ZN8Analyzer15setExpAvgFactorEi+22>:    blx 0x30508
0x000399ca <_ZN8Analyzer15setExpAvgFactorEi+26>:    fconstd d16, #7
0x000399ce <_ZN8Analyzer15setExpAvgFactorEi+30>:    vldr    d17, [pc, #32]  ; 0x399f2 <_ZN8Analyzer15setExpAvgFactorEi+66>

完整的源和这里汇编提供（因为它很短，基本上是2行的C ++。）

Full source and assembler available here (it's short, basically 2 lines of C++.)

您可以看到 0x399cc 是 fconstd 指令的中间。据<一href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204g/CJAEFGHE.html">arm.com该指令中添加了 VFP-V3 ，它应该（我认为）在任何现代的处理器使用。

You can see that 0x399cc is in the middle of the fconstd instruction. According to arm.com this instruction was added in VFP-v3, which should (I think) be available in any modern processor.

可能是什么回事？就因为地址是在中间的指示点到腐败的指针地方？ （请注意，回溯是非常合情合理的，所以它不喜欢这个功能，在某种程度上称为事故。）或者是其他什么东西？

What could be going on? Does the fact that the address is in the middle of an instruction point to a corrupt pointer somewhere? (Note that the backtrace makes perfect sense, so it's not like this function was somehow called on accident.) Or is it something else?

推荐答案

好吧，我知道了：NVIDIA的Tegra 2的只有16的64位GPU的寄存器，因此目标就必须编译使用 -mfpu =的VFPv3-D16 。有问题的指令使用寄存器 D16 ，这是实在太多了。 ：（

Ok, I got it: the NVIDIA Tegra 2 only has 16 64-bit GPU registers, and therefore to target it you must compile using -mfpu=vfpv3-d16. The instruction in question uses register d16, which is "just too many". :(

下面是引用到NVIDIA的论坛，员工提到这个限制：http://developer.nvidia.com/tegra/forum/optimal-performance-guidelines

Here is a reference to an NVIDIA forum where an employee mentions this limitation: http://developer.nvidia.com/tegra/forum/optimal-performance-guidelines

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