问题描述
我一直试图编写一个pintool来检测给定程序中的缓存命中和未命中.我发现有诸如INS_IsMemoryRead/Write之类的调用来确定指令是否为LD/ST.
I've been trying to write a pintool to instrument cache hits and misses in a given program.I found that there are calls such as INS_IsMemoryRead/Write to determine if the instruction is a LD/ST.
- 有没有一种方法可以确定指令是否发生高速缓存命中或未命中?
- 如果是这样，是否还可以获得从缓存/内存中获取数据所花费的周期数?
推荐答案
这两项都不可行.
pin附带的高速缓存工具"Memory"是一个非常简单的高速缓存功能模拟器.换句话说，通过使用缓存工具，可以根据缓存组织(例如大小，方式数量，缓存级别)查看/模拟应用程序可能有多少个缓存未命中.通过一些简单的代码编写，可以报告发生高速缓存未命中的指令，然后将这些指令映射回源代码.但是，即使将缓存模拟器配置为与真实系统具有相同的缓存组织，缓存模拟的命中/未命中结果也可能与真实计算机系统不同或相对应.
The cache tool, "Memory", which comes with pin is a very simple functional simulator of caches. Said in other words, by using the cache tool, one can see/simulate how many cache misses the application may have depending on the cache organization such as size, number of ways, cache levels. With some simple code writing it would be possible to report the instructions where the cache misses happen and later to map these instructions back to the source code. However, hit/miss results from the cache simulations may not be same as or correspond to the real computer systems even when the cache simulator is configured to have the same cache organization as the real system.
此外，缓存工具的另一个限制是它是单线程的.您不能将其用于多线程应用程序.
Also, one more limitation of the cache tool is that it is single threaded. You cannot use it for multi-threaded applications.
此外，将不可能获得任何时序信息，例如为缓存未命中所服务的周期数.这非常依赖于体系结构，我不知道可以从真实系统中提供此信息的工具.取而代之的是人们使用CPU时序模拟器. CPU时序模拟器的示例是Gem5 http://www.gem5.org/和基于PtlSim .
In addition, it will be impossible to get any timing information such as the number of cycles it takes to service a cache miss. This is very architecture dependent and I am not aware of a tool that can provide this information from the real system. Instead people use CPU timing simulators. Example CPU timing simulators are Gem5 http://www.gem5.org/ and Marss based on PtlSim http://marss86.org/.
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