问题描述
我正在尝试为 x86 上的一般保护错误 (GP#13) 编写 ISR.我无法从 INTEL 文档中弄清楚如何找出导致异常的错误地址.我知道对于页面错误异常 (GP#14),cr2 寄存器保存错误地址.任何帮助表示赞赏.
我在这里所做的所有参考都来自 在 评论,以防#GP
是由内存访问引起的,而您想要访问内存的地址,则需要对出错指令进行解码.
I am trying to write a ISR for the General Protection Fault (GP#13) on x86. I am unable to figure out from the INTEL docs as to how I can find out the faulting address causing the exception. I know that for Page fault exceptions (GP#14) the cr2 register holds the faulting address. Any help is appreciated.
All references I make here are from AMD64 Architecture Programmer's Manual Volume 2: System Programming, which also describes the legacy protected-mode (i.e., x86) behavior.
Figure 8-8 on page 240 shows the stack layout after an interrupt to the same privilege level (that is, the stack layout when an ISR is entered):
In Section 8.2.14, you can see that #GP
provides an error code and the following is also of interest:
The referenced section mentions the following:
So, unless you are using hardware task switching, the saved instruction pointer always point to the faulting instruction.
To get the address of the faulting instruction, simple get the saved EIP
and CS
values from the stack in your ISR. (If you're using a flat memory model and all your segments cover the whole 4GB, the saved CS
is of no interest, of course).
movl 4(%esp), %eax
movw 8(%esp), %ebx
Now, EAX
contains the saved EIP
and EBX
the saved CS
.
Edit: Of course, as pointed out by Alex in the comments, in case the #GP
was caused by a memory access and you want the address of the accessed memory, you will need to decode the faulting instruction.
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