Verilog For 循环数组乘法

问题描述

这似乎是一个相当愚蠢的问题，但从软件到 HDL 的过渡有时最初令人沮丧！

This may seem like a rather stupid question, but the transition from software to HDL's is sometimes rather frustrating initially!

我的问题:我想在 Verilog 中完成一个数组乘法.这是两个数组(逐点)的乘法，每个数组的长度为 200.以下代码在测试平台中运行良好:

My problem: I have an array multiplication I am trying to accomplish in Verilog. This is a multiplication of two arrays (point by point) which are of length 200 each. The following code worked fine in the testbench:

for (k=0; k<200; k=k+1)
    result <= result + A[k] * B[k];

但它甚至无法在 Verilog 模块中工作.我认为原因是因为操作应该在许多时钟周期内进行.由于如果我手动完成，它涉及写出 200 个乘法和 199 个加法 (！)，我想知道是否有使 for 循环工作(并且可合成)的技巧?

But it doesn't even come close to working in the Verilog module. I thought the reason was because the operation should take place over many many clock cycles. Since it involves writing out 200 multiplications and 199 additions if I do it by hand (!), I was wondering if there was a trick in making the for loop work (and be synthesizable)?

谢谢，

费萨尔.

推荐答案

您不想在那里使用 for 循环，而是想使用时钟逻辑块.For 循环仅用于描述不会对自身进行反馈的并行结构，它们很少有用，并且与您在软件程序中使用它们的类型不同.

You don't want to use a for loop there, you want to use a block of clocked logic. For loops are only for describing parallel structures that don't feedback on themselves, they are only rarely useful and not for the same kinds of things you would use them for in a software program.

要完成您想要实现的目标，您应该有一个像这样的块:

To do what you're trying to achieve, you should have a block like so:

always @(posedge clk or posedge reset)
    if (reset) begin
        result <= 0;
        k <= 0;
        result_done <= 0;
    end else begin
        result      <= result_done ? result : (result + A[k] * B[k]);
        k           <= result_done ?      k : k + 1;
        result_done <= result_done ?      1 : (k == 200);
    end
end

这在复位时将结果归零，将 A[k] * B[k] 添加到 200 个时钟的总和，然后在 k == 200 时停止计数并断言完成"信号.

This zeros the result on reset, adds A[k] * B[k] to a sum for 200 clocks, and then stops counting when k == 200 and asserts a 'done' signal.

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