零寄存器如何提高性能?

问题描述

在MIPS ISA中，有一个零寄存器($r0)，该寄存器始终提供零值.这使处理器能够:

In the MIPS ISA, there's a zero register ($r0) which always gives a value of zero. This allows the processor to:

1. 任何产生要丢弃结果的指令都可以将其目标定向到该寄存器
2. 成为0
的来源

1. Any instruction which produces result that is to be discarded can direct its target to this register
2. To be a source of 0

在此来源中说从而提高了CPU的速度.它如何提高性能?为什么不是所有的ISA都采用该零寄存器的原因是什么?

It is said in this source that this improved the speed of the CPU. How does it improve performance? And what are the reasons why not all ISA adopt this zero register?

MIPS的设计者使用了基准测试(用于确定 CPU的性能)，这使他们确信拥有寄存器 硬连线为0将提高CPU的性能(速度)，因为 反对没有它.并非所有人都同意将注册硬连线到 0是必不可少的，因此并非所有的ISA都有零寄存器.

The designers of MIPS used benchmarks (programs used to determine the performance of a CPU), which convinced them that having a register hardwired to 0 would improve the performance (speed) of the CPU as opposed to not having it. Not everyone agrees a register hardwired to 0 is essential, so not all ISAs have a zero register.

推荐答案

有几种潜在的方法可以提高性能；尚不清楚哪种处理器适用于该特定处理器，但我已按从大到小的顺序对它们进行了大致列出.

There's a few potential ways that this can improve performance; it's not clear which ones apply to that particular processor, but I've listed them roughly in order from most to least likely.

1. 它避免了虚假的管道停顿.如果没有显式的零寄存器，则必须取出一个寄存器，将其归零，然后使用其值.这意味着使用零的操作取决于清零操作，并且(取决于流水线转发系统的功能)可能取决于清零寄存器的先前值.像x86这样的体系结构具有非常小的危害分析工具，这些体系结构的寄存器文件非常小，并且基本上对其寄存器进行虚拟化处理，以防止问题产生. RISC处理器通常并非如此.
2. 如果某些操作可以避免读取寄存器，则它们可能更具流水线性.如果使用显式零寄存器，则操作数将为零的事实在指令解码阶段就知道了，而不是在寄存器提取阶段以后才知道.因此，可以跳过寄存器读取阶段.
类似地，显式丢弃结果的能力避免了寄存器写阶段的需要.
3. 当某些操作数之一为零或已知结果被丢弃时，某些操作可能会生成更简单的微代码.
4. 一个显式的零寄存器给编译器的优化器带来了一些压力，因为它不需要特别注意其寄存器分配(无需识别不会在读取或写入时造成停顿的寄存器). /li>

1. It avoids spurious pipeline stalls. Without an explicit zero register, it's necessary to take a register, zero it out, and use its value. This means that the zero-using operation is dependent on the zeroing operation, and (depending on how powerful the pipeline forwarding system is) possibly on the zeroed register's previous value. Architectures like x86, which have quite small register files and basically virtualize their registers to keep that from causing problems, have extremely powerful hazard analysis tools. The same is not generally true of RISC processors.
2. Certain operations may be more pipelineable if they can avoid a register read. If an explicit zero register is used, the fact that the operand will be zero is known at the instruction decode stage, rather than later on in the register fetch stage. Thus, the register read stage can be skipped.
3. Similarly, the ability to explicitly discard results avoids the need for a register write stage.
4. Certain operations may generate simpler microcode when one of their operands is known to be zero, or when the result is known to be discarded.
5. An explicit zero register takes some pressure off the compiler's optimizer, as it doesn't need to be as careful with its register assignment (no need to identify a register which won't cause a stall on read or write).

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