问题描述
在最近的Intel ISA文档中，已将 lfence 指令定义为序列化指令流（防止在其中执行乱序执行） 。特别是，指令的包括以下行：
In recent Intel ISA documents the lfence instruction has been defined as serializing the instruction stream (preventing out-of-order execution across it). In particular, the description of the instruction includes this line:
请注意，这不仅适用于 all 指令，还不仅适用于内存加载指令，还使 fences 不仅仅是一个内存排序栅栏。
Note that this applies to all instructions, not just memory load instructions, making lfence more than just a memory ordering fence.
尽管这现在出现在ISA文档中，但尚不清楚它是否是体系结构的，即是否被所有x86实现所遵循。特定于Intel。尤其是， AMD处理器还会将 fences 视为序列化指令流吗？
Although this now appears in the ISA documentation, it isn't clear if it is "architectural", i.e., to be obeyed by all x86 implementations, or if it is Intel specific. In particular, do AMD processors also treat lfence as serializing the instruction stream?
推荐答案
有一个配置此行为的MSR：
There is an MSR that configures that behaviour:
效果：当MSR位置1时遇到LFENCE时，分派将停止直到LFENCE
指令成为机器中最古老的指令。
Effect: Upon encountering an LFENCE when the MSR bit is set, dispatch will stop until the LFENCE instruction becomes the oldest instruction in the machine.
适用性：所有AMD系列10h / 12h / 14h / 15h / 16h / 17h处理器均支持此MSR。 LFENCE支持是
，由CPUID功能1 EDX位26 SSE2指示。 AMD系列0Fh / 11h处理器支持LFENCE，因为始终会序列化
，但不支持此MSR。 AMD计划支持此MSR，并为将来的所有
处理器访问此位。
Applicability: All AMD family 10h/12h/14h/15h/16h/17h processors support this MSR. LFENCE support is indicated by CPUID function1 EDX bit 26, SSE2. AMD family 0Fh/11h processors support LFENCE as serializing always but do not support this MSR. AMD plans support for this MSR and access to this bit for all future processors.
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