释放/获取语义wrt std :: mutex

问题描述

我正在阅读n3485中定义的C ++内存模型，并且讨论release / acquire语义，这从我所理解的，以及从定义：

，以防止写入释放的内存重新排序

会阻止当前读/写操作完成之前或之后的读/写操作的重新排序。第一个（获取）将确保当前正在完成的读取没有重新排序与在它之后的任何读取/写入，后者（释放）将确保当前写入不被重新排序与之前的读/写操作

现在可以说 std :: mutex :: lock / em>语义， std :: mutex :: unlock 本质上具有释义语义？

在标准中，我可以在

部分找到这个。

30.4.1.2互斥类型[thread.mutex.requirements.mutex] p>

根据我理解的在标准中定义，但是它似乎是一种发生在之前的关系，看看两个不同线程之间的两个语句评估，然而，从我的理解获取/释放语义，这有更多的与内存重新排序。 与同步也可以称为释放/获取语义？

因此，释放/获取语义不仅适用于加载/存储操作的重新排序，还有线程内交织操作？

在关于内存模型的标准部分中，它主要是关于有两个线程交织的有序关系。这留下了解释，这是否也适用于内存排序。

有人可以澄清吗？

解决方案

是，这是正确的。

很好，理论上1.10 / 8段可能意味着与同步的定义：

另一方面，这听起来不是一个非常正式的定义。但是，在1.10 / 10节中间接给出了一个更好的，虽然是隐含的：

由于至 关系的定义通常是对称的，我会说是依赖顺序先于 虽然你可能会正确地反对说明是非规范的;

我同意与同步的直觉是它发生在写（原子）操作之间由存储特定值的一个线程执行，以及读取该值的第一（原子）操作。该操作也可以在同一个线程中。

如果两个操作在不同的线程上，则同步与

$ b

30.4.1.2互斥类型[thread.mutex.requirements.mutex]

11同步：优先解锁（）

$（$）

对我来说，这似乎与上面的解释兼容。具有释放语义的操作（解锁，存储）将与获取语义的操作（锁定，加载）同步。

释放和获取语义描述一些操作的性质;与包含获取或释放语义的操作之间建立的关系（确实）关系是以明确定义的方式建立的。

因此，在某种意义上，同步与是这些操作的语义的结果，我们使用那些语义来实现正确的排序的指令，并限制CPU或编译器可能执行的重新排序。

I am reading the C++ memory model defined in n3485 and it talks about release/acquire semantics, which from what I understand, and also from the definitions given in this blog:

is going to prevent reordering of reads/writes before or after the current read/write being done. The first (acquire) will make sure that the read currently being done is not reordered with any read/write coming after it, the latter (release) will make sure that the current write is not being reordered with read/write operations that come before it.

Now can it be said that std::mutex::lock will have acquire semantics and that std::mutex::unlock essentially has release semantics?

In the Standard I can find this under section

30.4.1.2 Mutex types [thread.mutex.requirements.mutex]

From what I understand synchronize with is not explicitly defined in the standard, however it seems to be a type of happens before relation looking at two statements being evaluated between two different threads, however, from my understanding of acquire/release semantics, this has more to do with memory reordering. synchronize with could also be called release/acquire semantics?

So do release/acquire semantics apply not only to reordering of load/store operations and also intra-thread interleaving of operations?

In the standard section about the memory-model it mostly talks about ordered relations in terms of two threads interleaving. This leaves open to interpretation as to whether this applies also to memory ordering.

Can anybody clarify?

解决方案

Yes, this is correct.

Well, in theory Paragraph 1.10/8 is probably meant to give the definition of synchronizes with:

On the other hand, this does not sound like a very formal definition. However, a better, though implicit one is indirectly given in Paragraph 1.10/10:

Since the "is analogous to" relationship is most often symmetric, I would say that the above definition of "is-dependency-ordered before" indirectly provides a definition of "synchronizes with" as well - although you might correctly object that notes are non-normative; still, this seems to be the intended definition.

My intuition of the synchronizes with relationship is that it occurs between a write (atomic) operation performed by one thread that stores a certain value and the first (atomic) operation that reads that value. That operation might as well be in the same thread.

If the two operations are on different threads, then the synchronizes-with relation establishes a cross-thread ordering on operations.

To me, this seems compatible with the interpretation given above. An operation with release semantics (unlock, store) will synchronize with an operation of acquire semantics (lock, load).

Release and acquire semantics describe the nature of some operations; the synchronizes-with relationship is (indeed) a relationship which is established between operations that have acquire or release semantics, in a well-defined way.

So in a sense, synchronizes-with is a consequence of the semantics of those operations, and we use those semantics to achieve the correct ordering of instructions and constraint the possible reordering that the CPU or the compiler will perform.

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