如何在Verilog中逐行读取文本文件？

问题描述

我有一个SREC文件，它是一个简单的文本文件，我想在verilog中逐行读取它。我怎样才能做到这一点？

解决方案

以下是通过一个文件，每个时钟周期1行：期望的数据格式是一位小数每行数。

  integer data_file; //文件处理程序
整数scan_file; //文件处理程序
逻辑签名[21：0] captured_data; 
`define NULL 0 
 
 initial begin 
 data_file = $ fopen（data_file.dat，r）; 
 if（data_file ==`NULL）begin 
 $ display（data_file handle was NULL）; 
 $完成; 
 end 
 end 
 
总是@（posedge clk）begin 
 scan_file = $ fscanf（data_file，％d \ n，captured_data）; 
 if（！$ feof（data_file））begin 
 //使用被捕获的数据，就像你使用任何其他的wire或者reg的值一样。 
 end 
 end 
  

I have a SREC file which is a simple text file and I want to read it line by line in verilog. How can I do that?

解决方案

The following reads through a file, 1 line per clock cycle: expected data format is one decimal number per line.

integer               data_file    ; // file handler
integer               scan_file    ; // file handler
logic   signed [21:0] captured_data;
`define NULL 0

initial begin
  data_file = $fopen("data_file.dat", "r");
  if (data_file == `NULL) begin
    $display("data_file handle was NULL");
    $finish;
  end
end

always @(posedge clk) begin
  scan_file = $fscanf(data_file, "%d\n", captured_data);
  if (!$feof(data_file)) begin
    //use captured_data as you would any other wire or reg value;
  end
end

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