问题描述
我想交叉编译一个简单的程序，使用编译器的臂的linux-GCC套件ARM架构[臂的linux-GCC（Buildroot里面2011.08）4.3.6。我试图用一个简单的makefile编译C code，而另一简单的makefile编译C ++ code。例如，我对C code的makefile转载如下，但它并不适用于我的嵌入式系统上运行创造一个ELF二进制文件。主机系统是x64的GNU Linux操作系统。
I would like to cross-compile a simple program for ARM architecture using the arm-linux-gcc suite of compilers [arm-linux-gcc (Buildroot 2011.08) 4.3.6]. I've attempted to use a simple makefile for compiling C code, and another simple makefile for compiling C++ code. For example, my makefile for C code is reproduced below, but it does not create an ELF binary for running on my embedded system. The host system is x64 GNU Linux.
下面是我非常简单的makefile对于一个C程序列表：
Here is the listing of my very simple makefile for a C program:
CC=arm-linux-gcc
CFLAGS=-Wall
main: test.o
clean:
rm -f test test.o
以上仅供转载生成文件创建一个具有扩展的.o对象文件，并且不会创建一个ELF二进制文件。
The makefile reproduced above only creates an object file with extension .o, and does not create an ELF binary.
我GOOGLE了一个很好的解决方案，但我似乎无法找到一个网页显示例如交叉编译ARM的makefile用于C和C ++程序。也许回答这个职位可以证明这样的例子。
I've Googled for a good solution, but I can't seem to find one webpage showing example cross-compile ARM makefiles for both C and C++ programs. Perhaps an answer to this post could show such examples.
推荐答案
我想你的的Makefile 并改变了以下内容：
I tried your Makefile and changed the following:
test: test.o
它的工作后，这个改变并创建了一个名为测试二进制文件。它似乎有一个知道如何联系起来的一些隐含规则任何如果它的一个依赖是 whatever.o 。
It worked after this changed and created a binary called test. It seems that there is some implicit rule that knows how to link whatever if one of its dependencies is whatever.o.
另一种方式是明确列出的规则：
Another way is to list the rule explicitly:
main: test.o
$(CC) -o $@ $$
本使用特殊的宏 $ @ （指的目标的）和 $ （指的依赖的）。
This uses the special macros $@ (which means target) and $$ (which means dependencies).
这篇关于对于C / C ++的目标简单的makefile与ARM-Linux的使用gcc的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持！