请解释这些Verilog代码?

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问题描述

展位乘数的代码是:-

module ni(prod, a, b, busy, mc, mp, clk, start);
output [15:0] prod;
output [7:0] a, b;
output busy;
input [7:0] mc, mp;
input clk, start;
reg [7:0] A, Q, M;
reg Q_1;
reg [3:0] count;
wire [7:0] sum, difference;
always @(posedge clk)
begin
if (start) begin

A <= 8'b0;
M <= mc;
Q <= mp;
Q_1 <= 1'b0;

count <= 4'b0;
end
else begin

case ({Q[0], Q_1})
         2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
         2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
         default: {A, Q, Q_1} <= {A[7], A, Q};
      endcase




count <= count + 1'b1;
end
end
alu adder (sum, A, M, 1'b0);
alu subtracter (difference, A, ~M, 1'b1);
assign prod = {A, Q};
assign a = A;
assign b = Q ;
assign busy = (count < 8);
initial
  begin
    $monitor($time,"prod=%b, A=%b, Q=%b, Q_1=%b, M=%d, sum=%d, difference=%d, busy==%b, mc=%b, mp=%b, clk=%b, start=%b",
                      prod, A, Q, Q_1, M, sum,difference, busy, mc, mp, clk, start);
  end
endmodule
//The following is an alu.
//It is an adder, but capable of subtraction:
//Recall that subtraction means adding the two's complement--
//a - b = a + (-b) = a + (inverted b + 1)
//The 1 will be coming in as cin (carry-in)
module alu(out, a, b, cin);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;

assign out = a + b + cin;

endmodule

我想知道以下几行代码:-

i want to know how these lines of codes:-

case ({Q[0], Q_1})
             2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
             2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
             default: {A, Q, Q_1} <= {A[7], A, Q};
          endcase

解释以下逻辑:-

乘数和被乘数放在Q和分别为M个寄存器.还有一个1位寄存器逻辑上在Q寄存器的最低有效位(Q0)，指定为Q-1；它的用法将简要说明.乘法结果将出现在A和Q中寄存器. A和Q-1是初始化为0.与以前一样，控制逻辑扫描一次乘一.现在，在检查每个位时，也要检查其右边的位.如果两位是相同(1-1或0-0)，则A，Q和Q-1寄存器的所有位移到右边1位.如果两个位不同，则将被乘数加到或从A减去寄存器，取决于这两位是0-1还是1-0.下列的加法或减法，发生右移.无论哪种情况，右移使得最左边的位A的An-1，即An-1，不仅转移到An-2，而且还保留在An-1.这是必需的保留A和Q中数字的符号.它被称为算术移位，因为它保留了符号位.

the multiplier and multiplicand are placed in the Q andM registers, respectively. There is also a 1-bit register placedlogically to the right of theleast significant bit (Q0) of the Q register and designated Q-1; itsuse is explained shortly.The results of the multiplication will appear in the A and Qregisters. A and Q-1 areinitialized to 0. As before, control logic scans the bits of themultiplier one at a time.Now, as each bit is examined, the bit to its right is also examined.If the two bits are thesame (1-1 or 0-0), then all of the bits of the A, Q, and Q-1 registersare shifted to the right1 bit. If the two bits differ, then the multiplicand is added to orsubtracted from the Aregister, depending on whether the two bits are 0-1 or 1-0. Followingthe addition orsubtraction, the right shift occurs. In either case, the right shiftis such that the leftmost bitof A, namely An-1, not only is shifted into An-2, but also remains inAn-1. This is requiredto preserve the sign of the number in A and Q. It is known as anarithmetic shift, becauseit preserves the sign bit.

registers

请解释这些Verilog代码?

问题描述

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