ModelSim-Altera错误

本文介绍了ModelSim-Altera错误的处理方法，对大家解决问题具有一定的参考价值，需要的朋友们下面随着小编来一起学习吧！

问题描述

我正在将Ubuntu Linux 14.04 LTS与Altera Quartus 15.0 Web版一起使用，由于许可错误，我很难模拟我的设计.我正在为 VEEK-MT 的LCD触摸屏设计一个LCD驱动程序，使用 Cyclone IV EP4CE115 ，由Altera提供.

老实说，我对 ModelSim-Altera 之类的仿真软件没有太多经验，但是我确实知道如何使用 .vwf 文件并对其进行仿真，我也知道如何使用Signaltap逻辑分析仪.创建 usinversity程序.vwf 文件后，我编译项目，按 运行功能仿真 ，然后会出现一个包含以下内容的窗口:

I'm using Ubuntu Linux 14.04 LTS with Altera Quartus 15.0 web-edition and I'm having a hard time simulate my design due to licensing errors. I'm designing an LCD_driver for the VEEK-MT's LCD touch screen by terasic with the Cyclone IV EP4CE115 by Altera.

Honestly, I don't have much of experience with simulation software like ModelSim-Altera but I do know how to use .vwf files and simulate with them, I know as well how to use signaltap logic analyzer. After creating the usinversity program .vwf files, I compile the project, I press run functional simulation and I get a window with the following content:

使用:/home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin

Using: /home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin

要指定ModelSim可执行目录，请选择:工具->选项 -> EDA工具选项注意:如果同时提供ModelSim-Altera和ModelSim可执行文件，则将使用ModelSim-Altera.

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

****生成ModelSim Testbench ****

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --check_outputs = on --tool = modelsim_oem --format = verilog --write_settings_files = off test5 -c test5 --vector_source ="/path/to/Altera/projects/test/5/test5.vwf" --testbench_file ="/path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vt"

quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off test5 -c test5 --vector_source="/path/to/Altera/projects/test/5/test5.vwf" --testbench_file="/path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vt"

由ld.so检测到的不一致:dl-close.c:762:_dl_close:断言 `map-> l_init_Called'失败！信息: ****************************************************** *****************信息:正在运行Quartus II 64位EDA网表作者信息:版本15.0.0 版本145 04/22/2015 SJ网络版信息:版权所有(C)1991-2015 Altera公司.版权所有.信息:您对Altera的使用公司的设计工具，逻辑功能信息:及其他软件和工具及其AMPP合作伙伴逻辑信息:功能，以及上述任何信息的任何输出文件:(包括设备编程或仿真文件)，以及任何相关信息: 文档或信息明确是主题信息: Altera计划许可证信息的条款和条件: 订阅协议，Altera Quartus II许可协议，
信息:Altera MegaCore功能许可协议或其他
信息:适用的许可协议，包括但不限于
信息:您的使用仅出于编程逻辑的目的
信息:由Altera制造并由Altera或其
销售的设备信息:授权分销商.请参阅适用的
信息:协议以获取更多详细信息.信息:处理开始:太阳 2015年8月9日22:18:46信息:命令:quartus_eda --gen_testbench --check_outputs = on --tool = modelsim_oem --format = verilog --write_settings_files = off test5 -c test5 --vector_source =/path/to/Altera/projects/test/5/test5.vwf --testbench_file =/path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vt警告 (201007):在设计中找不到端口"h_counter"警告(201007):找不到在designWarning(201007)中找到端口"h_counter [10]":找不到端口 designWarning(201007)中的"h_counter [9]":找不到端口 designWarning(201007)中的"h_counter [8]":找不到端口 designWarning(201007)中的"h_counter [7]":找不到端口 designWarning(201007)中的"h_counter [6]":找不到端口 designWarning(201007)中的"h_counter [5]":找不到端口 designWarning(201007)中的"h_counter [4]":找不到端口 designWarning(201007)中的"h_counter [3]":找不到端口 designWarning(201007)中的"h_counter [2]":找不到端口 designWarning(201007)中的"h_counter [1]":找不到端口 designWarning(201007)中的"h_counter [0]":找不到端口"v_counter" 在designWarning(201007)中:在以下位置找不到端口"v_counter [9]" designWarning(201007):在以下位置找不到端口"v_counter [8]" designWarning(201007):在以下位置找不到端口"v_counter [7]" designWarning(201007):在以下位置找不到端口"v_counter [6]" designWarning(201007):在以下位置找不到端口"v_counter [5]" designWarning(201007):在以下位置找不到端口"v_counter [4]" designWarning(201007):在以下位置找不到端口"v_counter [3]" designWarning(201007):在以下位置找不到端口"v_counter [2]" designWarning(201007):在以下位置找不到端口"v_counter [1]" designWarning(201007):在以下位置找不到端口"v_counter [0]" designWarning(201007):在designWarning中找不到端口"HSD_s" (201007):在designInfo(201000)中找不到端口"VSD_s":已生成 Verilog测试平台文件 /path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vt 用于仿真信息:Quartus II 64位EDA网表编写器为成功的. 0个错误，25个警告信息:虚拟内存峰值:1088 兆字节信息:处理已结束:2015年8月9日22:18:47信息: 经过时间:00:00:01信息:总CPU时间(在所有处理器上): 00:00:01成功完成.

Inconsistency detected by ld.so: dl-close.c: 762: _dl_close: Assertion `map->l_init_called' failed! Info: *******************************************************************Info: Running Quartus II 64-Bit EDA Netlist Writer Info: Version 15.0.0 Build 145 04/22/2015 SJ Web Edition Info: Copyright (C) 1991-2015 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus II License Agreement,
Info: the Altera MegaCore Function License Agreement, or other
Info: applicable license agreement, including, without limitation,
Info: that your use is for the sole purpose of programming logic
Info: devices manufactured by Altera and sold by Altera or its
Info: authorized distributors. Please refer to the applicable
Info: agreement for further details. Info: Processing started: Sun Aug 9 22:18:46 2015Info: Command: quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off test5 -c test5 --vector_source=/path/to/Altera/projects/test/5/test5.vwf --testbench_file=/path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vtWarning (201007): Can't find port "h_counter" in designWarning (201007): Can't find port "h_counter[10]" in designWarning (201007): Can't find port "h_counter[9]" in designWarning (201007): Can't find port "h_counter[8]" in designWarning (201007): Can't find port "h_counter[7]" in designWarning (201007): Can't find port "h_counter[6]" in designWarning (201007): Can't find port "h_counter[5]" in designWarning (201007): Can't find port "h_counter[4]" in designWarning (201007): Can't find port "h_counter[3]" in designWarning (201007): Can't find port "h_counter[2]" in designWarning (201007): Can't find port "h_counter[1]" in designWarning (201007): Can't find port "h_counter[0]" in designWarning (201007): Can't find port "v_counter" in designWarning (201007): Can't find port "v_counter[9]" in designWarning (201007): Can't find port "v_counter[8]" in designWarning (201007): Can't find port "v_counter[7]" in designWarning (201007): Can't find port "v_counter[6]" in designWarning (201007): Can't find port "v_counter[5]" in designWarning (201007): Can't find port "v_counter[4]" in designWarning (201007): Can't find port "v_counter[3]" in designWarning (201007): Can't find port "v_counter[2]" in designWarning (201007): Can't find port "v_counter[1]" in designWarning (201007): Can't find port "v_counter[0]" in designWarning (201007): Can't find port "HSD_s" in designWarning (201007): Can't find port "VSD_s" in designInfo (201000): Generated Verilog Test Bench File /path/to/Altera/projects/test/5/simulation/qsim/test5.vwf.vt for simulationInfo: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 25 warnings Info: Peak virtual memory: 1088 megabytes Info: Processing ended: Sun Aug 9 22:18:47 2015 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully.

成功完成.

****生成功能仿真网表****

**** Generating the functional simulation netlist ****

quartus_eda --write_settings_files = off --functional = on --flatten_buses = off --simulation --tool = modelsim_oem --format = verilog --output_directory ="/path/to/Altera/projects/test/5/simulation/qsim/" test5 -c test5

quartus_eda --write_settings_files=off --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory="/path/to/Altera/projects/test/5/simulation/qsim/" test5 -c test5

****生成ModelSim .do脚本****

**** Generating the ModelSim .do script ****

/path/to/Altera/projects/test/5/simulation/qsim/test5.do 生成.

/path/to/Altera/projects/test/5/simulation/qsim/test5.do generated.

成功完成.

****运行ModelSim仿真****

**** Running the ModelSim simulation ****

/home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin/vsim -c -do test5.do

/home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin/../linux/vish: 加载共享库时出错:libXft.so.2:无法打开共享目标文件:没有这样的文件或目录错误.

/home/bdoronnb/Downloads/Quartus/15.0/ModelSim/modelsim_ase/bin/../linux/vish: error while loading shared libraries: libXft.so.2: cannot open shared object file: No such file or directory Error.

感谢您的帮助.

1991

ModelSim-Altera错误

问题描述

推荐答案