在 Verilog 中实现时序电路

问题描述

我正在尝试在 Verilog (Modelsim 10.4a)

I'm trying to implement the following Sequential Circuit in Verilog (Modelsim 10.4a)

这是我正在使用的代码

seq_circuit1.v

module seq_circuit1(x, clk, Q0, Q1);
 input x, clk;
 output Q0, Q1;
 reg J0,K0,J1,K1;
always @(negedge clk)
begin
 //Blocking and Non Blocking both will work
 J0 = Q1 & ~x;
 K0 = Q1 & x;
 J1 = x;
 K1 = (Q0 & x) || (~Q0 & ~x);
 jkfflop JKff0 (J0,K0,Q0);
 jkfflop JKff1 (J1,K1,Q1);
end
endmodule

jkfflop.v

module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;
 if(J==0 & K==1)
  begin
   assign Q = 0;
  end
 else if(J==1 & K==0)
  begin
   assign Q = 1;
  end
 else if(J==1 & K==1)
  begin
   assign Q = ~Q;
  end
endmodule

我遇到了一些错误，我无法弄清楚原因.谁能告诉我我哪里做错了..

I'm getting some errors and I'm unable to figure out why. Can anybody tell me where did I do it wrong..

推荐答案

seq_circuit1

• 您不能在 always 块内实例化子模块(您的 FF).将它们移到外面，无论是在之前还是之后.
• 您的 jkfflop 实例缺少 clk 输入信号.
• 根据您的图表，您对 FF 的输入应该是组合逻辑，而不是顺序逻辑，因此应该使用 always @(*) 块，而不是时钟块.

• You can't instantiate submodules (your FFs) inside an always block.Move them outside, either before or after.
• Your instantiations for jkfflop are missing the clk input signal.
• based on your diagram, your inputs to the FFs should be combinational logic, not sequential, and should therefore use an always @(*) block, not a clocked one.

jkfflop

verilog 中的
• if 语句仅在 generate、always 或 inital 块内有效.由于这是一个 FF，你需要一个 always @(posedge clk) 或 always @(negedge clk)
• 如果使用 always 块，请将 assign 语句替换为非阻塞赋值 (<=).我们在这里使用 NBA 代替阻塞赋值 (=)，因为它是一个边缘触发的阻塞.
• 如果在 always 块内为 Q 赋值，请将 output Q 更改为 output reg Q

• if statements in verilog are only valid inside a generate, always or inital block. Since this is a FF, you'll want an always @(posedge clk) or always @(negedge clk)
• If using an always block, replace the assign statements with non-blocking assignments (<=). We use NBA's here instead of a blocking assignments (=), as it's an edge-triggered block.
• If assigning a value to Q inside an always block, change output Q to output reg Q

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