问题描述
我首先要说我不是该领域的专家，我的问题可能包含误解，在这种情况下，如果您纠正我并附上资源，我会很高兴，以便我可以了解更多细节.
I will first say that I'm not expert in the field and my question might contain misunderstanding, in which case, I'll be glad if you correct me and attach resources so I can learn further details.
我试图弄清楚系统总线的方式以及移动设备中出现的各种设备(如传感器芯片、wifi/BT SoC、触摸屏等)如何被 CPU 寻址(和其他 MCU).
I'm trying to figure out the way that the system bus and how the various devices that appear in a mobile device (such as sensors chips, wifi/BT SoC, touch panel, etc.) are addressed by the CPU (and by other MCUs).
在 PC 世界中，我们有将命令/数据路由到设备的总线仲裁器，而且，afaik，地址是硬连线在板上(如果我错了，请纠正我).但是，在移动世界中，我没有找到任何此类寻址的证据.我确实发现 ARM 已经标准化了 高级微控制器总线架构，不过我不知道，该标准是否适用于位于同一 SoC(即 Exynos、OMAP、Snapdragon 等)内的组件(cpu-cores)或也影响外围接口.具体来说，我问的是哪个组件负责为外围设备和 MMIO 地址分配地址?
In the PC world we have the bus arbitrator that route the commands/data to the devices, and, afaik, the addresses are hardwired on the board (correct me if I'm wrong). However, in the mobile world I didn't find any evidence of that type of addressing; I did find that ARM has standardized the Advanced Microcontroller Bus Architecture, I don't know, though, whether that standard applied for the components (cpu-cores) which lies inside the same SoC (that is Exynos, OMAP, Snapdragon etc.) or also influence peripheral interfaces. Specifically I'm asking what component is responsible on allocating addresses to peripheral devices and MMIO addresses?
一个更基本的问题是移动设备架构中是否存在总线管理，或者是否存在某种星形"拓扑(CPU 为中心).
A more basic question would be whether there even exist a bus management in the mobile device architecture or maybe there is some kind of "star" topology (where the CPU is the center).
从 这个问题我得到这些设备被视为平台设备的印象，即直接连接到 CPU 的设备，而不是通过总线.不过，我的问题是操作系统如何知道如何解决它们?然后是其他线程，this 和这个关于平台设备/drivers 让我很困惑..
From this question I get the impression that these devices are considered as platform devices, i.e., devices that are connected directly to the CPU, and not through a bus. Still, my question is how does the OS knows how to address them? Then other threads, this and this about platform devices/drivers made me confused..
推荐答案
ARM 和 x86 的区别在于 PIO.ARM 上没有访问 I/O 设备的特殊指令.一切都是通过内存映射 I/O 完成的.
A difference between ARM and the x86 is PIO. There are no special instruction on the ARM to access an I/O device. Everything is done through memory mapped I/O.
第二个区别是 ARM(和一般的 RISC)有一个独立的加载/存储单元，与普通逻辑分开.
A second difference is the ARM (and RISC in general) has a separate load/store unit(s) that are separate from normal logic.
第三个区别是 ARM 许可 架构 和逻辑核心.第一个被 Apple、Samsung 等公司使用，它们制造了无尘室版本的内核.对于实际购买逻辑的第二组，ARM CPU 将包含来自 AMBA 系列的东西.
A third difference is that ARM licenses both the architecture and logic core. The first is used by companies like Apple, Samsung, etc who make a clean room version of the cores. For the second set, who actually buy the logic, the ARM CPU will include something from the AMBA family.
ARM 的其他外设，例如 GIC(Cortex-A 中断控制器)、NVIC(Cortex-M 中断控制器)、L2 控制器、UART 等，都将带有 AMBA 类型的接口.第 3 方公司(ChipIdea USB 等)也可以为特定 ARM 总线设置逻辑.
Other peripherals from ARM such as a GIC (Cortex-A interrupt controller), NVIC (Cortex-M interrupt controller), L2 controllers, UARTs, etc will all come with an AMBA type interface. 3rd party companies (ChipIdea USB, etc) may also make logic that is setup for a specific ARM bus.
注意 Wikipedia 上的 AMBA 记录了几种总线类型.
Note AMBA at Wikipedia documents several bus types.
- APB - 低速外围总线；有点像南桥.
- AHB - 多个版本(旧的北桥).
- AXI - 一种较新的多 CPU(主)高速总线.示例 NIC301.
- ACE - AXI 扩展.
- APB - a lower speed peripheral bus; sort of like south bridge.
- AHB - several versions (older north bridge).
- AXI - a newer multi-CPU (master) high speed bus. Example NIC301.
- ACE - an AXI extension.
单个 CPU/内核可能有一个、两个或多个主连接到 AXI 总线.可能有多个内核连接到 AXI 总线.核心的 load/store 和 instruction fetch 单元可以使用多个端口将请求分派到单独的从属设备.SOC 供应商将平衡端口数量与预期的内存带宽需求.GPU 也经常与 DDR 从机一起连接到 AXI BUS.
A single CPU/core may have one, two, or more master connection to an AXI bus. There maybe multiple cores attached to the AXI bus. The load/store and instruction fetch units of a core can use the multiple ports to dispatch requests to separate slaves. The SOC vendor will balance the number of ports with expected memory bandwidth needs. GPUs are also often connected to the AXI BUS along with DDR slaves.
确实没有100%的标准拓扑；特别是如果您考虑所有可能的未来 ARM 设计.然而，典型的拓扑结构将包括一个顶级 AXI 和一些 AHB 外围设备.一个或多个第二级 APB(总线)将提供对低速外围设备的访问.并非每个 SOC 供应商都愿意花时间重新设计外设，而旧的 AHB 接口速度对于设备来说可能相当不错.
It is true that there is no 100% standard topology; especially if you consider all possible future ARM designs. However, typical topologies will include a top level AXI with some AHB peripherals attached. One or multiple 2nd level APB (buses) will provide access to low speed peripherals. Not every SOC vendor wants to spend time to redesign peripherals and the older AHB interface speeds maybe quite fine for a device.
您的问题已标记为 embedded-linux.在大多数情况下，Linux 只需要知道物理地址.有时，外围总线控制器可能需要配置.例如，可以将 APB 配置为允许或禁止用户模式.此配置可以在引导时锁定.一般来说，Linux 不会直接过多关心总线结构.程序员可能已经编写了具有结构知识的驱动程序(例如 IRAM 更快等).
Your question is tagged embedded-linux. For the most part Linux just needs to know the physical addresses. On occasion, the peripheral BUS controllers may need configuration. For instance, an APB may be configure to allow or disallow user mode. This configuration could be locked at boot time. Generally, Linux doesn't care too much about the bus structure directly. Programmers may have coded a driver with knowledge of the structure (like IRAM is fasters, etc).
不过，我的问题是操作系统如何知道如何解决这些问题?
较旧的 Linux 内核将这些定义放在一个机器文件中，并传递一个平台资源结构，包括中断号和寄存器组的物理地址.在较新的 Linux 版本中，此信息包含在 Open Firmware 或 设备树 文件中.
Older Linux kernels put these definitions in a machine file and passed a platform resource structure including interrupt number, and the physical address of a register bank. In newer Linux versions, this information is included with Open Firmware or device tree files.
具体来说，我问的是哪个组件负责为外围设备和 MMIO 地址分配地址?
物理地址由 SOC 制造商设置.Linux 平台支持 将使用 MMU 将它们作为不可缓存映射到某些未使用的范围.通常物理地址可能非常稀疏，因此虚拟重映射包更密集.每个都会导致 TLB 命中(MMU 缓存).
The physical addresses are set by the SOC manufacturer. Linux platform support will use the MMU to map them as non-cacheable to some un-used range. Often the physical addresses may be very sparse so the virtual remapping pack more densely. Each one incurs a TLB hit (MMU cache).
这是一个使用 AXI 并连接了 Cortex-M 和 Cortex-A 的示例 SOC 总线结构.
Here is a sample SOC bus structure using AXI with a Cortex-M and Cortex-A connected.
PBRIDGE 组件是 APB 网桥，并以星形拓扑连接.正如其他人所建议的那样，您需要查看特定的 SOC 文档以了解详细信息.但是，如果您没有 SOC 并试图大致了解 ARM，那么无论您拥有什么 SOC，上述一些信息都会对您有所帮助.
The PBRIDGE components are APB bridges and it is connected in a star topology. As others suggests, you need to look a your particular SOC documentation for specifics. However, if you have no SOC and are trying to understand ARM generally, some of the information above will help you, no matter what SOC you have.
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