为什么我得到“实体端口 d 与组件 portParsing 的无符号类型不匹配..."?当我尝试模拟这个 VHDL 时?

问题描述

完整的错误信息是:

ERROR:HDLCompiler:377 - "C:/Users/einar/Documents/Xilinx/ISE/Projects/EDA385/scale_clock_tb.vhd" Line 17: Entity port d does not match with type unsigned of component port

我正在使用 ISE webpack 并且我已经实现了顶层模块，顶层模块是 scale_clock.

I'm using ISE web pack and I have implemented the top module, the top module is scale_clock.

此外，当我进行行为模拟时，它模拟得很好.但是对于 post-map 或 post-route，我收到了上面的错误消息.

Also, it simulates just fine when I do behavioral simulation. But for post-map or post-route I get the error message above.

这是组件的代码:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-----------------------------------------
-- scale_clock entity declaration --
-----------------------------------------
ENTITY scale_clock IS
  GENERIC (n_bits : INTEGER := 10);
  PORT
  (
    clk_i  : IN  STD_LOGIC;
    load   : IN  STD_LOGIC;
    d      : IN  UNSIGNED (n_bits-1 DOWNTO 0) := (OTHERS => '0');
    clk_o  : OUT STD_LOGIC
  );
END scale_clock;

----------------------------------------------
-- scale_clock architecture definition --
----------------------------------------------
ARCHITECTURE behavioral OF scale_clock IS
  SIGNAL new_clk : STD_LOGIC := '0';

BEGIN
  clk_o <= new_clk;

  clk_gen: PROCESS(clk_i, load, d) -- Should load and d be in the stvty list? --
    VARIABLE cnt : UNSIGNED (n_bits-1 DOWNTO 0) := (0 => '1', OTHERS => '0');
    VARIABLE top : UNSIGNED (n_bits-1 DOWNTO 0) := (OTHERS => '0');
  BEGIN
    IF (rising_edge(clk_i)) THEN
      IF (load = '1') THEN
      -- Syncrounous load of prescaler value. --
        top     := d;
        cnt     := (0 => '1', OTHERS => '0');
        new_clk <= '0';
      ELSIF (cnt = top) THEN
        cnt     := (0 => '1', OTHERS => '0');
        new_clk <= NOT new_clk;
      ELSE
      -- Count up. --
        cnt := cnt + 1;
      END IF;
    END IF;
  END PROCESS;
END ARCHITECTURE;

这是测试平台:

-- TestBench Template
LIBRARY ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY scale_clock_testbench IS
END scale_clock_testbench ;

ARCHITECTURE behavior OF scale_clock_testbench  IS

-- Component Declaration
  COMPONENT scale_clock
  PORT
  (
    clk_i : IN STD_LOGIC;
    load  : IN STD_LOGIC;
    d     : IN UNSIGNED (9 DOWNTO 0) := (OTHERS => '0');
    clk_o : OUT STD_LOGIC
  );
  END COMPONENT;

  SIGNAL  clk_i :  STD_LOGIC := '0';
  SIGNAL  load  :  STD_LOGIC := '0';
  SIGNAL  d     :  UNSIGNED (9 DOWNTO 0) := (OTHERS => '0');
  SIGNAL  clk_o :  STD_LOGIC := '0';

  CONSTANT CLK_PERIOD : TIME := 10 ns;

BEGIN

-- Component Instantiation
  uut: scale_clock PORT MAP
  (
    clk_i =>    clk_i,
    load  =>    load,
    d     =>    d,
    clk_o =>    clk_o
  );

  clk_process : PROCESS
  BEGIN
    clk_i   <=    '0';
    WAIT FOR CLK_PERIOD/2;
    clk_i   <=    '1';
    WAIT FOR CLK_PERIOD/2;
  END PROCESS;



--  Test Bench Statements
   tb : PROCESS
   BEGIN

      WAIT FOR 100 ns; -- wait until global set/reset completes

      -- Add user defined stimulus here

      WAIT FOR CLK_PERIOD * 3;
      d     <=  ("0100101100"); -- decimal 300 in binary --
      load  <= '1';
      WAIT FOR CLK_PERIOD * 1;
      load  <= '0';


      wait; -- will wait forever
   END PROCESS tb;
--  End Test Bench

END;

我是 VHDL 的新手，但对我来说它们似乎很匹配.请指教.

I'm new to VHDL but to me they seem to match just fine. Please advice.

推荐答案

在 Tsukuyo 的回答中(几乎)正确识别了问题.也就是说，综合(和 P&R)的 OUTPUT 到处都包含 std_logic[_vector]，如果您尝试模拟这些文件，您的测试平台连接需要匹配它们的类型.

The problem is (almost) correctly identified in Tsukuyo's answer. Namely that the OUTPUT from synthesis (and P&R) contains std_logic[_vector] everywhere, and if you try to simulate these files, your testbench connections need to match their types.

Xilinx 工具试图将一个糟糕的 解决方案强加给您，即到处使用std_logic[_vector]，而不是让设计和测试平台真正反映设计的意图.在某种程度上，如果您让它为模块自动生成测试平台，它将有帮助地"将您的所有端口类型(如果您使用枚举或记录，通常是错误的！)转换为 std_logic[_vector].

Xilinx tools try to force a terrible solution on you, namely to use std_logic[_vector] everywhere instead of making the design and testbench actually reflect the design's intent. To the extent that if you let it auto-generate a testbench for a module, it will "helpfully" convert all your port types (often incorrectly if you use enumerations or records!) into std_logic[_vector].

更好的解决方案 (IMO) 是按照它们应有的方式编写模块和测试平台 - 即在您可以达到的最高级别(而不是浪费时间在低级别上乱搞).不仅无符号，而且枚举、整数、布尔值和记录都是可合成的.

A better solution (IMO) is to write both your modules and testbench the way they ought to be - namely at the highest level you can (instead of wasting time messing around at low level). Not only unsigned, but enumerations, integers, booleans and records are synthesisable.

然后(如果您需要进行路由后模拟)围绕自动生成的 std_logic 版本编写一个简单的包装器，它将其所有端口转换为正确的类型，并在您的测试平台中实例化该包装器.

Then (if you need to do a post-route simulation) write a simple wrapper around the auto-generated std_logic version, which converts all its ports to the correct types, and instantiate that wrapper in your testbench.

这篇关于为什么我得到“实体端口 d 与组件 portParsing 的无符号类型不匹配..."?当我尝试模拟这个 VHDL 时?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持！