问题描述
我有两个进程 A 和 B，每个进程都有自己的时钟输入.
I have two processes A and B, each with its own clock input.
时钟频率略有不同，因此不同步.
The clock frequencies are a little different, and therefore not synchronized.
进程 A 从一个 IC 采样数据，这个数据需要传递给进程 B，然后需要将这个数据写入另一个 IC.
Process A samples data from an IC, this data needs to be passed to process B, which then needs to write this data to another IC.
我目前的解决方案是在进程 A 和 B 之间使用一些简单的握手信号.内存已声明为进程 A 内的分布式 RAM(128 字节为 std_logic_vector(7 downto 0) 数组)(不是块内存).
My current solution is using some simple handshake signals between process A and B.The memory has been declared as distributed RAM (128Bytes as an array of std_logic_vector(7 downto 0)) inside process A (not block memory).
我使用的是 Xilinx 的 Spartan 3AN 和 ISE Webpack.
I'm using a Spartan 3AN from Xilinx and the ISE Webpack.
但这是正确的做法吗?
我在某处读到 Spartan 3 具有支持两个时钟的双端口块内存，那么这是否更正确?
I read somewhere that the Spartan 3 has dual-port block memory supporting two clocks, so would this be more correct?
我之所以这么问，是因为我的设计行为不可预测，在这种情况下，我只是讨厌魔法.:-)
The reason I'm asking, is because my design behaves unpredictable, and in cases like this I just hate magic. :-)
推荐答案
除了非常特殊的例外情况，在两个独立时钟域之间移动数据的唯一正确方法是使用异步 FIFO(也更正确地称为多路速率FIFO).
Except for very specific exceptional cases, the only correct way to move data between two independent clock domains is to use an asynchronous FIFO (also more correctly called a multi-rate FIFO).
在几乎所有 FPGA(包括您使用的 Xilinx 部件)中，您都可以使用供应商创建的 FIFO——在 Xilinx 的情况下，您可以通过使用 CoreGen 工具自己生成一个 FIFO 来实现这一点.
In almost all FPGAs (including the Xilinx parts you are using), you can use FIFOs created by the vendor -- in Xilinx's case, you do this by generating yourself a FIFO using the CoreGen tool.
您也可以使用双端口 RAM 和适当的握手逻辑自己构建这样的 FIFO，但与大多数事情一样，除非您有充分的理由这样做，否则您不应该自己重新发明.
You can also construct such a FIFO yourself using a dual-port RAM and appropriate handshaking logic, but like most things, this is not something you ought to go reinvent on your own unless you have a very good reason to do so.
您还可以考虑您的设计是否真的需要具有多个时钟域.有时这是绝对必要的，但这比大多数刚开始相信的人很多要少得多.例如，即使您需要以多种速率运行的逻辑，您通常也可以通过使用单个时钟和适当生成的同步时钟使能来处理此问题.
You also might consider whether your design really needs to have multiple clock domains. Sometimes it's absolutely necessary, but that's much, MUCH less often than most people just starting out believe. For instance, even if you need logic that runs at multiple rates, you can often handle this by using a single clock and appropriately generated synchronous clock enables.
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